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https://github.com/openhwgroup/cvw
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56 lines
2.4 KiB
Systemverilog
56 lines
2.4 KiB
Systemverilog
///////////////////////////////////////////
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// dtim.sv
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//
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// Written: Rose Thompson rose@rosethompson.net
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// Created: 30 January 2022
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// Modified: 18 January 2023
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//
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// Purpose: tightly integrated memory into the LSU.
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//
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// Documentation: RISC-V System on Chip Design
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module dtim import cvw::*; #(parameter cvw_t P) (
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input logic clk, reset,
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input logic FlushW,
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input logic ce, // Chip Enable. 0: Holds ReadDataWordM
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input logic [1:0] MemRWM, // Read/Write control
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input logic [P.PA_BITS-1:0] DTIMAdr, // No stall: Execution stage memory address. Stall: Memory stage memory address
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input logic [P.LLEN-1:0] WriteDataM, // Write data from IEU
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input logic [P.LLEN/8-1:0] ByteMaskM, // Selects which bytes within a word to write
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output logic [P.LLEN-1:0] ReadDataWordM // Read data before subword selection
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);
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logic we;
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localparam LLENBYTES = P.LLEN/8;
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// verilator lint_off WIDTH
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localparam DEPTH = P.DTIM_RANGE/LLENBYTES;
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// verilator lint_on WIDTH
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localparam ADDR_WDITH = $clog2(DEPTH);
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localparam OFFSET = $clog2(LLENBYTES);
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assign we = MemRWM[0] & ~FlushW; // have to ignore write if Trap.
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ram1p1rwbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(DEPTH), .WIDTH(P.LLEN))
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ram(.clk, .ce, .we, .bwe(ByteMaskM), .addr(DTIMAdr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM), .din(WriteDataM));
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endmodule
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