mirror of
https://github.com/openhwgroup/cvw
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171 lines
8.8 KiB
Systemverilog
171 lines
8.8 KiB
Systemverilog
///////////////////////////////////////////
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// loggers.sv
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//
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// Written: Rose Thompson rose@rosethompson.net
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// Modified: 24 July 2024
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//
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// Purpose: Wraps all the synthesizable rvvi hardware into a single module for the testbench.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module rvvitbwrapper import cvw::*; #(parameter cvw_t P,
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parameter MAX_CSRS = 5,
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parameter logic [31:0] RVVI_INIT_TIME_OUT = 32'd4,
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parameter logic [31:0] RVVI_PACKET_DELAY = 32'd2)(
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input logic clk,
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input logic reset,
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output logic RVVIStall,
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input logic mii_tx_clk,
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output logic [3:0] mii_txd,
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output logic mii_tx_en, mii_tx_er,
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input logic mii_rx_clk,
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input logic [3:0] mii_rxd,
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input logic mii_rx_dv,
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input logic mii_rx_er
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);
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logic valid;
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logic [72+(5*P.XLEN) + MAX_CSRS*(P.XLEN+16)-1:0] rvvi;
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localparam TOTAL_CSRS = 36;
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// pipeline controlls
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logic StallE, StallM, StallW, FlushE, FlushM, FlushW;
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// required
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logic [P.XLEN-1:0] PCM;
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logic InstrValidM;
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logic [31:0] InstrRawD;
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logic [63:0] Mcycle, Minstret;
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logic TrapM;
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logic [1:0] PrivilegeModeW;
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// registers gpr and fpr
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logic GPRWen, FPRWen;
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logic [4:0] GPRAddr, FPRAddr;
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logic [P.XLEN-1:0] GPRValue, FPRValue;
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logic [P.XLEN-1:0] CSRArray [TOTAL_CSRS-1:0];
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// axi 4 write data channel
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logic [31:0] RvviAxiWdata;
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logic [3:0] RvviAxiWstrb;
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logic RvviAxiWlast;
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logic RvviAxiWvalid;
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logic RvviAxiWready;
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logic tx_error_underflow, tx_fifo_overflow, tx_fifo_bad_frame, tx_fifo_good_frame, rx_error_bad_frame;
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logic rx_error_bad_fcs, rx_fifo_overflow, rx_fifo_bad_frame, rx_fifo_good_frame;
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logic MiiTxEnDelay;
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logic EthernetTXCounterEn;
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logic [31:0] EthernetTXCount;
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assign StallE = dut.core.StallE;
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assign StallM = dut.core.StallM;
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assign StallW = dut.core.StallW;
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assign FlushE = dut.core.FlushE;
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assign FlushM = dut.core.FlushM;
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assign FlushW = dut.core.FlushW;
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assign InstrValidM = dut.core.ieu.InstrValidM;
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assign InstrRawD = dut.core.ifu.InstrRawD;
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assign PCM = dut.core.ifu.PCM;
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assign Mcycle = dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0];
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assign Minstret = dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2];
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assign TrapM = dut.core.TrapM;
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assign PrivilegeModeW = dut.core.priv.priv.privmode.PrivilegeModeW;
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assign GPRAddr = dut.core.ieu.dp.regf.a3;
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assign GPRWen = dut.core.ieu.dp.regf.we3;
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assign GPRValue = dut.core.ieu.dp.regf.wd3;
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assign FPRAddr = dut.core.fpu.fpu.fregfile.a4;
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assign FPRWen = dut.core.fpu.fpu.fregfile.we4;
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assign FPRValue = dut.core.fpu.fpu.fregfile.wd4;
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assign CSRArray[0] = dut.core.priv.priv.csr.csrm.MSTATUS_REGW; // 12'h300
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assign CSRArray[1] = dut.core.priv.priv.csr.csrm.MSTATUSH_REGW; // 12'h310
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assign CSRArray[2] = dut.core.priv.priv.csr.csrm.MTVEC_REGW; // 12'h305
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assign CSRArray[3] = dut.core.priv.priv.csr.csrm.MEPC_REGW; // 12'h341
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assign CSRArray[4] = dut.core.priv.priv.csr.csrm.MCOUNTEREN_REGW; // 12'h306
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assign CSRArray[5] = dut.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW; // 12'h320
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assign CSRArray[6] = dut.core.priv.priv.csr.csrm.MEDELEG_REGW; // 12'h302
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assign CSRArray[7] = dut.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h303
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assign CSRArray[8] = dut.core.priv.priv.csr.csrm.MIP_REGW; // 12'h344
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assign CSRArray[9] = dut.core.priv.priv.csr.csrm.MIE_REGW; // 12'h304
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assign CSRArray[10] = dut.core.priv.priv.csr.csrm.MISA_REGW; // 12'h301
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assign CSRArray[11] = dut.core.priv.priv.csr.csrm.MENVCFG_REGW; // 12'h30A
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assign CSRArray[12] = dut.core.priv.priv.csr.csrm.MHARTID_REGW; // 12'hF14
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assign CSRArray[13] = dut.core.priv.priv.csr.csrm.MSCRATCH_REGW; // 12'h340
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assign CSRArray[14] = dut.core.priv.priv.csr.csrm.MCAUSE_REGW; // 12'h342
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assign CSRArray[15] = dut.core.priv.priv.csr.csrm.MTVAL_REGW; // 12'h343
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assign CSRArray[16] = 0; // 12'hF11
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assign CSRArray[17] = 0; // 12'hF12
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assign CSRArray[18] = {{P.XLEN-12{1'b0}}, 12'h100}; //P.XLEN'h100; // 12'hF13
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assign CSRArray[19] = 0; // 12'hF15
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assign CSRArray[20] = 0; // 12'h34A
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// supervisor CSRs
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assign CSRArray[21] = dut.core.priv.priv.csr.csrs.csrs.SSTATUS_REGW; // 12'h100
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assign CSRArray[22] = dut.core.priv.priv.csr.csrm.MIE_REGW & 12'h222; // 12'h104
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assign CSRArray[23] = dut.core.priv.priv.csr.csrs.csrs.STVEC_REGW; // 12'h105
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assign CSRArray[24] = dut.core.priv.priv.csr.csrs.csrs.SEPC_REGW; // 12'h141
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assign CSRArray[25] = dut.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW; // 12'h106
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assign CSRArray[26] = dut.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW; // 12'h10A
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assign CSRArray[27] = dut.core.priv.priv.csr.csrs.csrs.SATP_REGW; // 12'h180
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assign CSRArray[28] = dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW; // 12'h140
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assign CSRArray[29] = dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW; // 12'h143
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assign CSRArray[30] = dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW; // 12'h142
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assign CSRArray[31] = dut.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & dut.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h144
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assign CSRArray[32] = dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW; // 12'h14D
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// user CSRs
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assign CSRArray[33] = dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW; // 12'h001
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assign CSRArray[34] = dut.core.priv.priv.csr.csru.csru.FRM_REGW; // 12'h002
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assign CSRArray[35] = {dut.core.priv.priv.csr.csru.csru.FRM_REGW, dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW}; // 12'h003
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rvvisynth #(P, MAX_CSRS, TOTAL_CSRS) rvvisynth(.clk, .reset, .StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW,
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.PCM, .InstrValidM, .InstrRawD, .Mcycle, .Minstret, .TrapM,
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.PrivilegeModeW, .GPRWen, .FPRWen, .GPRAddr, .FPRAddr, .GPRValue, .FPRValue, .CSRArray,
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.valid, .rvvi);
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packetizer #(P, MAX_CSRS, RVVI_INIT_TIME_OUT, RVVI_PACKET_DELAY) packetizer(.rvvi, .valid, .m_axi_aclk(clk), .m_axi_aresetn(~reset), .RVVIStall,
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.RvviAxiWdata, .RvviAxiWstrb, .RvviAxiWlast, .RvviAxiWvalid, .RvviAxiWready);
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eth_mac_mii_fifo #("GENERIC", "BUFG", 32) ethernet(.rst(reset), .logic_clk(clk), .logic_rst(reset),
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.tx_axis_tdata(RvviAxiWdata), .tx_axis_tkeep(RvviAxiWstrb), .tx_axis_tvalid(RvviAxiWvalid), .tx_axis_tready(RvviAxiWready),
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.tx_axis_tlast(RvviAxiWlast), .tx_axis_tuser('0), .rx_axis_tdata(), .rx_axis_tkeep(), .rx_axis_tvalid(), .rx_axis_tready(1'b1),
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.rx_axis_tlast(), .rx_axis_tuser(),
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.mii_rx_clk(clk),
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.mii_rxd('0),
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.mii_rx_dv('0),
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.mii_rx_er('0),
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.mii_tx_clk(clk),
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.mii_txd,
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.mii_tx_en,
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.mii_tx_er,
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// status
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.tx_error_underflow, .tx_fifo_overflow, .tx_fifo_bad_frame, .tx_fifo_good_frame, .rx_error_bad_frame,
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.rx_error_bad_fcs, .rx_fifo_overflow, .rx_fifo_bad_frame, .rx_fifo_good_frame,
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.cfg_ifg(8'd12), .cfg_tx_enable(1'b1), .cfg_rx_enable(1'b1));
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flopr #(1) txedgereg(clk, reset, mii_tx_en, MiiTxEnDelay);
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assign EthernetTXCounterEn = ~mii_tx_en & MiiTxEnDelay;
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counter #(32) ethernexttxcounter(clk, reset, EthernetTXCounterEn, EthernetTXCount);
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endmodule
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