David Harris 8b854bb1c2 Cleaned up LINT erors		2021-10-23 06:28:49 -07:00
..
csr.sv	Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.	2021-09-15 13:14:00 -04:00
csrc.sv	Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.	2021-09-15 13:14:00 -04:00
csri.sv	fixed bug where M mode was sensitive to S mode traps	2021-09-07 19:14:39 -04:00
csrm.sv	Changed some flops to settable	2021-10-18 17:05:29 -07:00
csrn.sv	Gave names to for loops in generate blocks for ease of reference	2021-07-04 18:52:16 -04:00
csrs.sv	Changed some flops to settable	2021-10-18 17:05:29 -07:00
csrsr.sv	fixed the read timer issue but we still have problems with interrupts and i/o devices.	2021-08-06 10:16:06 -05:00
csru.sv	Cleaned up LINT erors	2021-10-23 06:28:49 -07:00
privdec.sv	Implemented TSR, TW, TVM, MXR status bits	2021-07-06 01:32:05 -04:00
privileged.sv	Modified the preformance counter's InstRet to include ECALL and EBREAK by changing the hazard logic so these instructions don't self flush the W stage.	2021-08-23 15:46:17 -05:00
trap.sv	Fixed MTVAL contents during breakpoint. Now all riscv-arch-test vectors pass in rv32 and rv64	2021-09-13 12:40:40 -04:00