Rose Thompson 1345a0f315 Merge branch 'main' of https://github.com/openhwgroup/cvw		2024-09-24 10:13:50 -05:00
..
checksignature.sv	Significant refactoring of testbench.	2023-06-14 17:02:49 -05:00
DCacheFlushFSM.sv	Updated my name in multiple locations.	2024-08-21 10:50:39 -07:00
functionName.sv	Updated my name in multiple locations.	2024-08-21 10:50:39 -07:00
instrNameDecTB.sv	Eliminate more logical operators and replace with bitwise	2024-05-15 10:50:23 -07:00
instrTrackerTB.sv	More code cleanup	2024-06-14 09:50:07 -07:00
loggers.sv	More name updates.	2024-08-21 10:51:24 -07:00
ramxdetector.sv	Yay! I got verilator to compile our testbench! Does it actually work I don't know.	2023-12-18 16:44:34 -06:00
riscvassertions.sv	Depricate conditional generation based on A_SUPPORTED, which is now computed from ZALRSC_SUPPORTED and ZAAMO_SUPPORTED	2024-08-08 05:27:35 -07:00
rvvitbwrapper.sv	Added padding into the hw rvvi format.	2024-08-06 18:34:46 -05:00
wallyTracer.sv	Fixed wallyTracer floating-point register FLEN	2024-08-29 11:11:19 -07:00
watchdog.sv	Updated my name in multiple locations.	2024-08-21 10:50:39 -07:00