David Harris 75b8e1f68e Fixed lint for RV32IC by handling PMP_ENTRIES = 0 in csrm, but may have broken buildroot.		2021-12-30 02:38:42 +00:00
..
cache	Moved LSU Bus interface control path into it's own module.	2021-12-29 17:35:45 -06:00
ebu	Changed the bus name between dcache and ebu.	2021-12-28 15:57:36 -06:00
fpu	all FCVT imperas tests pass	2021-12-30 00:19:40 +00:00
generic	Merge branch 'main' into fpga	2021-11-29 10:06:53 -06:00
hazard	Added proper credit to Richard Davis, the author of the original sd card reader.	2021-12-12 15:05:50 -06:00
ieu	ALUControl cleanup	2021-12-19 13:53:45 -08:00
ifu	Removed WalkerInstrPageFault from icache, privilege unit, lsu, and hptw.	2021-12-28 12:33:07 -06:00
lsu	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-12-30 00:53:44 +00:00
mmu	rv32i regression and linting	2021-12-30 00:53:39 +00:00
muldiv	Moved generate statements for optional units into wallypipelinedhart	2021-12-19 16:53:41 -08:00
privileged	Fixed lint for RV32IC by handling PMP_ENTRIES = 0 in csrm, but may have broken buildroot.	2021-12-30 02:38:42 +00:00
sdc	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-12-29 20:18:06 -06:00
uncore	Oups missed files in the last commit.	2021-12-15 10:25:08 -06:00
wally	Fixed interrupt delay bug by reverting CommittedM changes.	2021-12-28 22:27:12 -06:00