Ross Thompson 7139279e50 Moved more logic inside the dcache memory.		2021-08-25 13:17:07 -05:00
..
cache-sram.sv	A few more cache fixes	2021-04-13 01:07:40 -04:00
cacheLRU.sv	simplified or_rows generation and renamed oneHotDecoder to onehotdecoder	2021-08-25 06:46:41 -04:00
dcache_ptw_interaction_README.txt	Added documentation about how the dcache and ptw interact.	2021-08-12 18:05:36 -05:00
dcache.sv	Moved more logic inside the dcache memory.	2021-08-25 13:17:07 -05:00
DCacheMem.sv	Moved more logic inside the dcache memory.	2021-08-25 13:17:07 -05:00
dmapped.sv	Gave names to for loops in generate blocks for ease of reference	2021-07-04 18:52:16 -04:00
icache.sv	Parameterized I$/D$ configurations and added sanity check assertions in testbench	2021-07-20 08:57:13 -04:00
ICacheCntrl.sv	Removed the hardware page table walker fault state from the icache so that the icache will only unstall CPU for 1 cycle.	2021-07-22 19:42:19 -05:00
ICacheMem.sv	Partial implementation of the data cache. Missing the fsm.	2021-07-07 17:52:16 -05:00
sram1rw.sv	change sram1rw to have a small delay so that we don't have signals changing on clock edges	2021-07-19 11:30:07 -04:00