mirror of
https://github.com/openhwgroup/cvw
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87 lines
4.2 KiB
Systemverilog
87 lines
4.2 KiB
Systemverilog
///////////////////////////////////////////
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// controllerinput.sv
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//
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// Written: Rose Thompson rose@rosethompson.net
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// Created: August 31, 2022
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// Modified: 18 January 2023
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//
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// Purpose: AHB multi controller interface to merge LSU and IFU controls.
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// See ARM_HIH0033A_AMBA_AHB-Lite_SPEC 1.0
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// Arbitrates requests from instruction and data streams
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// Connects core to peripherals and I/O pins on SOC
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// Bus width presently matches XLEN
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//
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// Documentation: RISC-V System on Chip Design
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module controllerinput #(
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parameter PA_BITS,
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parameter SAVE_ENABLED = 1 // 1: Save manager inputs if Save = 1, 0: Don't save inputs
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)(
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input logic HCLK,
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input logic HRESETn,
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input logic Save, // Two or more managers requesting (HTRANS != 00) at the same time. Save the non-granted manager inputs
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input logic Restore, // Restore a saved manager inputs when it is finally granted
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input logic Disable, // Suppress HREADY to the non-granted manager
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output logic Request, // This manager is making a request
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// controller input
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input logic [1:0] HTRANSIn, // Manager input. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
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input logic HWRITEIn, // Manager input. AHB 0: Read operation 1: Write operation
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input logic [2:0] HSIZEIn, // Manager input. AHB transaction width
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input logic [2:0] HBURSTIn, // Manager input. AHB burst length
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input logic [PA_BITS-1:0] HADDRIn, // Manager input. AHB address
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output logic HREADYOut, // Indicate to manager the peripheral is not busy and another manager does not have priority
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// controller output
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output logic [1:0] HTRANSOut, // Arbitrated manager transaction. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
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output logic HWRITEOut, // Arbitrated manager transaction. AHB 0: Read operation 1: Write operation
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output logic [2:0] HSIZEOut, // Arbitrated manager transaction. AHB transaction width
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output logic [2:0] HBURSTOut, // Arbitrated manager transaction. AHB burst length
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output logic [PA_BITS-1:0] HADDROut, // Arbitrated manager transaction. AHB address
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input logic HREADYIn // Peripheral ready
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);
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logic HWRITESave;
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logic [2:0] HSIZESave;
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logic [2:0] HBURSTSave;
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logic [1:0] HTRANSSave;
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logic [PA_BITS-1:0] HADDRSave;
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if (SAVE_ENABLED) begin
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flopenr #(1+3+3+2+PA_BITS) SaveReg(HCLK, ~HRESETn, Save,
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{HWRITEIn, HSIZEIn, HBURSTIn, HTRANSIn, HADDRIn},
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{HWRITESave, HSIZESave, HBURSTSave, HTRANSSave, HADDRSave});
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mux2 #(1+3+3+2+PA_BITS) RestorMux({HWRITEIn, HSIZEIn, HBURSTIn, HTRANSIn, HADDRIn},
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{HWRITESave, HSIZESave, HBURSTSave, HTRANSSave, HADDRSave},
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Restore,
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{HWRITEOut, HSIZEOut, HBURSTOut, HTRANSOut, HADDROut});
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end else begin
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assign HWRITEOut = HWRITEIn;
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assign HSIZEOut = HSIZEIn;
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assign HBURSTOut = HBURSTIn;
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assign HTRANSOut = HTRANSIn;
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assign HADDROut = HADDRIn;
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end
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assign Request = HTRANSOut != 2'b00;
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assign HREADYOut = HREADYIn & ~Disable;
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endmodule
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