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106 lines
5.0 KiB
Systemverilog
106 lines
5.0 KiB
Systemverilog
///////////////////////////////////////////
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// cvtshiftcalc.sv
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//
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// Written: me@KatherineParry.com
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// Modified: 7/5/2022
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//
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// Purpose: Conversion shift calculation
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//
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// Documentation: RISC-V System on Chip Design Chapter 13
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module cvtshiftcalc import cvw::*; #(parameter cvw_t P) (
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input logic XZero, // is the input zero?
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input logic ToInt, // to integer conversion?
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input logic IntToFp, // interger to floating point conversion?
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input logic [P.FMTBITS-1:0] OutFmt, // output format
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input logic [P.NE:0] CvtCe, // the calculated expoent
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input logic [P.NF:0] Xm, // input mantissas
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input logic [P.CVTLEN-1:0] CvtLzcIn, // input to the Leading Zero Counter (without msb)
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input logic CvtResSubnormUf, // is the conversion result subnormal or underlows
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output logic CvtResUf, // does the cvt result unerflow
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output logic [P.CVTLEN+P.NF:0] CvtShiftIn // number to be shifted
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);
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logic [$clog2(P.NF):0] ResNegNF; // the result's fraction length negated (-NF)
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///////////////////////////////////////////////////////////////////////////
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// shifter
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///////////////////////////////////////////////////////////////////////////
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// seclect the input to the shifter
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// fp -> int:
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// | P.XLEN zeros | mantissa | 0's if nessisary |
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// .
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// Other problems:
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// - if shifting to the right (neg CalcExp) then don't a 1 in the round bit (to prevent an incorrect plus 1 later durring rounding)
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// - we do however want to keep the one in the sticky bit so set one of bits in the sticky bit area to 1
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// - ex: for the case 0010000.... (double)
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// ??? -> fp:
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// - if result is subnormal or underflowed then we want to shift right i.e. shift right then shift left:
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// | P.NF-1 zeros | mantissa | 0's if nessisary |
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// .
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// - otherwise:
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// | LzcInM | 0's if nessisary |
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// .
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// change to int shift to the left one
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always_comb
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// get rid of round bit if needed
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// | add sticky bit if needed
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// | |
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if (ToInt) CvtShiftIn = {{P.XLEN{1'b0}}, Xm[P.NF]&~CvtCe[P.NE], Xm[P.NF-1]|(CvtCe[P.NE]&Xm[P.NF]), Xm[P.NF-2:0], {P.CVTLEN-P.XLEN{1'b0}}};
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else if (CvtResSubnormUf) CvtShiftIn = {{P.NF-1{1'b0}}, Xm, {P.CVTLEN-P.NF+1{1'b0}}};
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else CvtShiftIn = {CvtLzcIn, {P.NF+1{1'b0}}};
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// choose the negative of the fraction size
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if (P.FPSIZES == 1) begin
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assign ResNegNF = -($clog2(P.NF)+1)'(P.NF);
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end else if (P.FPSIZES == 2) begin
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assign ResNegNF = OutFmt ? -($clog2(P.NF)+1)'(P.NF) : -($clog2(P.NF)+1)'(P.NF1);
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end else if (P.FPSIZES == 3) begin
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always_comb
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case (OutFmt)
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P.FMT: ResNegNF = -($clog2(P.NF)+1)'(P.NF);
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P.FMT1: ResNegNF = -($clog2(P.NF)+1)'(P.NF1);
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P.FMT2: ResNegNF = -($clog2(P.NF)+1)'(P.NF2);
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default: ResNegNF = 'x;
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endcase
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end else if (P.FPSIZES == 4) begin
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always_comb
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case (OutFmt)
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2'h3: ResNegNF = -($clog2(P.NF)+1)'(P.Q_NF);
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2'h1: ResNegNF = -($clog2(P.NF)+1)'(P.D_NF);
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2'h0: ResNegNF = -($clog2(P.NF)+1)'(P.S_NF);
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2'h2: ResNegNF = -($clog2(P.NF)+1)'(P.H_NF);
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endcase
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end
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// determine if the result underflows ??? -> fp
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// - if the first 1 is shifted out of the result then the result underflows
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// - can't underflow an integer to fp conversions
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assign CvtResUf = ($signed(CvtCe) < $signed({{P.NE-$clog2(P.NF){1'b1}}, ResNegNF}))&~XZero&~IntToFp;
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endmodule
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