cvw/examples/verilog/fulladder/verilate

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#verilator --timescale "1ns/1ns" --timing -cc --exe --build --top-module testbench fulladder.sv
#verilator --timescale "1ns/1ns" --timing -cc --exe --top-module testbench fulladder.sv
#verilator --binary --top-module testbench fulladder.sv
verilator --timescale "1ns/1ns" --timing --binary --top-module testbench fulladder.sv