mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-03 18:25:27 +00:00
6 lines
327 B
Plaintext
6 lines
327 B
Plaintext
|
#verilator --timescale "1ns/1ns" --timing -cc --exe --build --top-module testbench fulladder.sv
|
||
|
|
#verilator --timescale "1ns/1ns" --timing -cc --exe --top-module testbench fulladder.sv
|
||
|
|
#verilator --binary --top-module testbench fulladder.sv
|
||
|
|
verilator --timescale "1ns/1ns" --timing --binary --top-module testbench fulladder.sv
|
||
|
|
|