Ross Thompson 67ef46ea92 Partially working byte write enables. Works for cache, but not dtim or bus only.		2022-03-10 16:11:39 -06:00
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cache	Partially working byte write enables. Works for cache, but not dtim or bus only.	2022-03-10 16:11:39 -06:00
ebu	Started make allsynth to try many experiments	2022-02-17 17:57:02 +00:00
fma	Refactored SRAM bit write enable	2022-03-09 17:49:28 +00:00
fpu	Renamed unpacking unit to unpack and renamed WriteDataW to ResultW in IEU datapath	2022-02-28 20:50:51 +00:00
generic	RAM simplification	2022-02-08 20:15:23 +00:00
hazard	Renamed LSUStall to LSUStallM	2022-01-15 00:24:16 +00:00
ieu	LSU/Cache code review notes	2022-03-04 00:07:31 +00:00
ifu	Added byte write enables to cache SRAMs.	2022-03-10 15:48:31 -06:00
lsu	Partially working byte write enables. Works for cache, but not dtim or bus only.	2022-03-10 16:11:39 -06:00
mmu	adrdecs comments	2022-02-28 20:33:41 +00:00
muldiv	Better solution to the integer divider interrupt interaction.	2022-01-12 14:22:18 -06:00
privileged	but apparently QEMU doesn't show UXL in SSTATUS	2022-03-02 22:44:19 +00:00
uncore	Partially working byte write enables. Works for cache, but not dtim or bus only.	2022-03-10 16:11:39 -06:00
wally	Broken state. address translation not working after changes to hptw to support atomic updates to PT.	2022-02-16 23:37:36 -06:00
sdc	piplined directory cleanup	2022-01-07 12:43:50 +00:00