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slack-notifier
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added instructions to slack notifier
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2022-05-18 16:50:31 -07:00 |
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wave-dos
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Renamed wallypipelinedhart to wallypipelinedcore
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2022-01-20 16:02:08 +00:00 |
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wkdir
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added wkdir in regression so regression runs out of box (assuming the old version of arch tests)
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2022-05-17 20:32:38 +00:00 |
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buildrootBugFinder.py
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update to match new filesystem organization
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2022-03-26 21:28:32 +00:00 |
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fp.do
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moved lzc to generic and small optimizations on fcvt
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2022-05-27 09:04:02 -07:00 |
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fpga-wave.do
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Fixed the SDC clock divider so it actually can work during reset. This will enable the fpga to operate at a faster clock while the SDC is < 10Mhz.
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2022-04-04 09:57:26 -05:00 |
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lint-wally
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fpu paramaterized - except fdivsqrt
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2022-06-02 19:50:28 +00:00 |
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linux-wave.do
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small signs of life on new interrupt spoofing
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2022-04-08 12:32:30 -07:00 |
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make-tests.sh
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simplified make-tests.sh to run the current makefile in regression
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2022-05-17 17:29:34 -07:00 |
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Makefile
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Fixed fma files to stop breaking synthesis. Changed Makefiles to skip Imperas
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2022-03-03 15:38:08 +00:00 |
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makefile-memfile
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Fixed fma files to stop breaking synthesis. Changed Makefiles to skip Imperas
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2022-03-03 15:38:08 +00:00 |
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regression-wally
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added a todo to riscv-wally so that long buildroot looks for a successful boot rather than a specific instruction
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2022-05-25 17:40:57 -07:00 |
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sim-buildroot
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switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv
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2022-03-01 03:11:43 +00:00 |
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sim-buildroot-batch
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switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv
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2022-03-01 03:11:43 +00:00 |
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sim-coremark-batch
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sim-fp
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Fixed unpacker bug LT EQ LE pass testfloat
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2022-05-20 17:19:50 +00:00 |
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sim-fp64
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sim-fp64-batch
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sim-fp-batch
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added unpackinput.sv
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2022-05-31 16:18:50 +00:00 |
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sim-wally
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single and double conversions pass all tests
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2022-05-25 23:02:02 +00:00 |
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sim-wally-batch
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Fixed unpacker bug LT EQ LE pass testfloat
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2022-05-20 17:19:50 +00:00 |
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wally-coremark.do
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wally-fp64-batch.do
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wally-fp64.do
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wally-harvard.do
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Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.
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2022-01-13 22:21:43 -06:00 |
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wally-pipelined-batch.do
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Revert "Added parameter to keep tracking on for buildroot and buildroot-checkpoint in regression.py"
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2022-06-02 12:41:01 -07:00 |
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wally-pipelined-fpga.do
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fpga simulation works again.
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2022-04-03 17:31:07 -05:00 |
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wally-pipelined.do
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Revert "parametrized linux testbench's DEBUG_TRACE and added parameters to relevant calls of the linux testbench in wally-pipelined.do"
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2022-06-02 12:45:21 -07:00 |
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wave-all.do
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Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.
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2022-01-27 17:11:27 -06:00 |
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wave-coremark.do
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More cache cleanup.
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2022-02-13 15:47:27 -06:00 |
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wave-fpu.do
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Added fp tests - doesnpass yet
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2022-05-19 16:32:30 +00:00 |
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wave.do
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removed delapidated signals SIE_REGW SIP_REGW TimerIntM SwIntM
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2022-05-31 20:10:56 +00:00 |
