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229 lines
10 KiB
Systemverilog
229 lines
10 KiB
Systemverilog
///////////////////////////////////////////
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// privileged.sv
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//
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// Written: David_Harris@hmc.edu 5 January 2021
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// Modified:
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//
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// Purpose: Implements the CSRs, Exceptions, and Privileged operations
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// See RISC-V Privileged Mode Specification 20190608
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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// SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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// *** remove signals not needed by PMA/PMP now that it is moved
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module privileged (
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input logic clk, reset,
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input logic FlushD, FlushE, FlushM, FlushW, StallD, StallE, StallM, StallW,
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(* mark_debug = "true" *) input logic CSRReadM, CSRWriteM,
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input logic [`XLEN-1:0] SrcAM,
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input logic [`XLEN-1:0] PCM,
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input logic [31:0] InstrM,
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output logic [`XLEN-1:0] CSRReadValW,
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output logic [`XLEN-1:0] PrivilegedNextPCM,
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output logic RetM, TrapM,
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output logic ITLBFlushF, DTLBFlushM,
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input logic InstrValidM, CommittedM, DivE,
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input logic FRegWriteM, LoadStallD,
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input logic BPPredDirWrongM,
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input logic BTBPredPCWrongM,
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input logic RASPredPCWrongM,
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input logic BPPredClassNonCFIWrongM,
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input logic [4:0] InstrClassM,
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input logic DCacheMiss,
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input logic DCacheAccess,
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input logic ICacheMiss,
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input logic ICacheAccess,
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input logic PrivilegedM,
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input logic InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM,
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input logic InstrMisalignedFaultM, IllegalIEUInstrFaultD, IllegalFPUInstrD,
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input logic LoadMisalignedFaultM,
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input logic StoreAmoMisalignedFaultM,
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input logic TimerIntM, MExtIntM, SExtIntM, SwIntM,
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input logic [63:0] MTIME_CLINT,
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input logic [`XLEN-1:0] InstrMisalignedAdrM, IEUAdrM,
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input logic [4:0] SetFflagsM,
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// Trap signals from pmp/pma in mmu
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// *** do these need to be split up into one for dmem and one for ifu?
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// instead, could we only care about the instr and F pins that come from ifu and only care about the load/store and m pins that come from dmem?
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input logic InstrAccessFaultF,
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input logic LoadAccessFaultM,
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input logic StoreAmoAccessFaultM,
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output logic ExceptionM,
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output logic IllegalFPUInstrE,
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output logic [1:0] PrivilegeModeW,
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output logic [`XLEN-1:0] SATP_REGW,
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output logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
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output logic [1:0] STATUS_MPP,
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output var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
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output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0],
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output logic [2:0] FRM_REGW,
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output logic BreakpointFaultM, EcallFaultM
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);
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logic [1:0] NextPrivilegeModeM;
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logic [`XLEN-1:0] CauseM, NextFaultMtvalM;
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logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, STVEC_REGW, MTVEC_REGW;
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logic [`XLEN-1:0] MEDELEG_REGW;
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logic [11:0] MIDELEG_REGW;
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logic sretM, mretM, ecallM, ebreakM, wfiM, sfencevmaM;
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logic IllegalCSRAccessM;
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logic IllegalIEUInstrFaultE, IllegalIEUInstrFaultM;
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logic IllegalFPUInstrM;
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logic InstrPageFaultD, InstrPageFaultE, InstrPageFaultM;
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logic InstrAccessFaultD, InstrAccessFaultE, InstrAccessFaultM;
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logic IllegalInstrFaultM, TrappedSRETM;
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logic MTrapM, STrapM, UTrapM;
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(* mark_debug = "true" *) logic InterruptM;
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logic STATUS_SPP, STATUS_TSR, STATUS_TW;
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logic STATUS_MIE, STATUS_SIE;
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logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW;
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logic md;
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logic StallMQ;
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///////////////////////////////////////////
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// track the current privilege level
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///////////////////////////////////////////
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// get bits of DELEG registers based on CAUSE
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assign md = CauseM[`XLEN-1] ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM[`LOG_XLEN-1:0]];
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// PrivilegeMode FSM
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always_comb begin
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TrappedSRETM = 0;
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if (mretM) NextPrivilegeModeM = STATUS_MPP;
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else if (sretM)
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if (STATUS_TSR & PrivilegeModeW == `S_MODE) begin
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TrappedSRETM = 1;
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NextPrivilegeModeM = PrivilegeModeW;
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end else NextPrivilegeModeM = {1'b0, STATUS_SPP};
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else if (TrapM) begin // Change privilege based on DELEG registers (see 3.1.8)
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if (`S_SUPPORTED & md & (PrivilegeModeW == `U_MODE | PrivilegeModeW == `S_MODE))
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NextPrivilegeModeM = `S_MODE;
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else NextPrivilegeModeM = `M_MODE;
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end else NextPrivilegeModeM = PrivilegeModeW;
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end
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flopenl #(2) privmodereg(clk, reset, ~StallW, NextPrivilegeModeM, `M_MODE, PrivilegeModeW);
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// *** WFI could be implemented here and depends on TW
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///////////////////////////////////////////
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// decode privileged instructions
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///////////////////////////////////////////
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privdec pmd(.InstrM(InstrM[31:20]),
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.PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM, .TrappedSRETM,
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.PrivilegeModeW, .STATUS_TSR, .IllegalInstrFaultM,
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.sretM, .mretM, .ecallM, .ebreakM, .wfiM, .sfencevmaM);
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///////////////////////////////////////////
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// Control and Status Registers
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///////////////////////////////////////////
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csr csr(.clk, .reset,
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.FlushE, .FlushM, .FlushW,
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.StallE, .StallM, .StallW,
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.InstrM, .PCM, .SrcAM,
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.CSRReadM, .CSRWriteM, .TrapM, .MTrapM, .STrapM, .UTrapM, .mretM, .sretM,
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.TimerIntM, .MExtIntM, .SExtIntM, .SwIntM,
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.MTIME_CLINT,
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.InstrValidM, .FRegWriteM, .LoadStallD,
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.BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM,
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.BPPredClassNonCFIWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
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.NextPrivilegeModeM, .PrivilegeModeW,
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.CauseM, .NextFaultMtvalM, .STATUS_MPP,
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.STATUS_SPP, .STATUS_TSR,
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.MEPC_REGW, .SEPC_REGW, .STVEC_REGW, .MTVEC_REGW,
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.MEDELEG_REGW,
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.SATP_REGW,
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.MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .MIDELEG_REGW,
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.STATUS_MIE, .STATUS_SIE,
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.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TW,
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.PMPCFG_ARRAY_REGW,
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.PMPADDR_ARRAY_REGW,
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.SetFflagsM,
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.FRM_REGW,
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.CSRReadValW,
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.IllegalCSRAccessM);
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///////////////////////////////////////////
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// Extract exceptions by name and handle them
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///////////////////////////////////////////
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assign BreakpointFaultM = ebreakM; // could have other causes too
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assign EcallFaultM = ecallM;
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flopr #(1) StallMReg(.clk, .reset, .d(StallM), .q(StallMQ));
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assign ITLBFlushF = sfencevmaM & ~StallMQ;
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assign DTLBFlushM = sfencevmaM;
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// sets ITLBFlush to pulse for one cycle of the sfence.vma instruction
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// In this instr we want to flush the tlb and then do a pagetable walk to update the itlb and continue the program.
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// But we're still in the stalled sfence instruction, so if itlbflushf == sfencevmaM, tlbflush would never drop and
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// the tlbwrite would never take place after the pagetable walk. by adding in ~StallMQ, we are able to drop itlbflush
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// after a cycle AND pulse it for another cycle on any further back-to-back sfences.
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// A page fault might occur because of insufficient privilege during a TLB
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// lookup or a improperly formatted page table during walking
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// pipeline fault signals
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flopenrc #(2) faultregD(clk, reset, FlushD, ~StallD,
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{InstrPageFaultF, InstrAccessFaultF},
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{InstrPageFaultD, InstrAccessFaultD});
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flopenrc #(4) faultregE(clk, reset, FlushE, ~StallE,
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{IllegalIEUInstrFaultD, InstrPageFaultD, InstrAccessFaultD, IllegalFPUInstrD}, // ** vs IllegalInstrFaultInD
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{IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE, IllegalFPUInstrE});
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flopenrc #(4) faultregM(clk, reset, FlushM, ~StallM,
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{IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE, IllegalFPUInstrE},
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{IllegalIEUInstrFaultM, InstrPageFaultM, InstrAccessFaultM, IllegalFPUInstrM});
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// *** it should be possible to combine some of these faults earlier to reduce module boundary crossings and save flops dh 5 july 2021
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trap trap(.clk, .reset,
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.InstrMisalignedFaultM, .InstrAccessFaultM, .IllegalInstrFaultM,
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.BreakpointFaultM, .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
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.LoadAccessFaultM, .StoreAmoAccessFaultM, .EcallFaultM, .InstrPageFaultM,
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.LoadPageFaultM, .StoreAmoPageFaultM,
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.mretM, .sretM,
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.PrivilegeModeW, .NextPrivilegeModeM,
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.MEPC_REGW, .SEPC_REGW, .STVEC_REGW, .MTVEC_REGW,
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.MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .MIDELEG_REGW,
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.STATUS_MIE, .STATUS_SIE,
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.PCM,
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.InstrMisalignedAdrM, .IEUAdrM,
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.InstrM,
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.InstrValidM, .CommittedM, .DivE,
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.TrapM, .MTrapM, .STrapM, .UTrapM, .RetM,
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.InterruptM,
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.ExceptionM,
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.PrivilegedNextPCM, .CauseM, .NextFaultMtvalM);
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endmodule
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