cvw/fpga/constraints
2024-05-30 15:48:27 -05:00
..
artyddr3.ucf
constraints-ArtyA7.xdc
constraints-vcu108.xdc
constraints-vcu118.xdc
debug2.xdc
debug4.xdc
debug6.xdc The vcu108 works again. Added renumber.py script that renumbers probes in an xdc file. 2024-05-30 15:48:27 -05:00
marked_debug_all.txt The vcu108 works again. Added renumber.py script that renumbers probes in an xdc file. 2024-05-30 15:48:27 -05:00
marked_debug_small.txt
marked_debug.txt
small-debug.xdc Replaced fpga's verilog top with system verilog. 2023-12-15 13:42:52 -06:00
vcu-small-debug.xdc