mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
314 lines
12 KiB
ArmAsm
314 lines
12 KiB
ArmAsm
///////////////////////////////////////////
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// ebu.S
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//
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// Written: David_Harris@hmc.edu 21 January 2024
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//
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// Purpose: Test coverage for EBU
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// load code to initalize stack, handle interrupts, terminate
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#include "WALLY-init-lib.h"
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# run-elf.bash find this in project description
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main:
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li t5, 0x1
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slli t5, t5, 62
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ori t5, t5, 0xF0
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csrs menvcfg, t5 # menvcfg.PBMTE = 1, CBZE, CBCFE, CBIE all 1
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# Page table root address at 0x80010000; SV48
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li t5, 0x9000000000080010
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csrw satp, t5
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# sfence.vma x0, x0
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# switch to supervisor mode
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li a0, 1
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ecall
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#
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# Tricky case to cover. I$ miss concurrent with DTLB miss. HPTW has to hit the first
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# access in the cache and miss a later one. Trigger this by doing a load that touches
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# a page not in the DTLB but where the top-level PTE is already there. Has to happen
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# near the end of the 16-instruction I$ line.
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#
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# Condition Coverage for instance /core/ebu/ebu/ebufsmarb --
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#
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# File ../src/ebu/ebufsmarb.sv
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#----------------Focused Condition View-------------------
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#Line 72 Item 1 ((HREADY & FinalBeatD) & (LSUReq ~& IFUReq))
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#Condition totals: 2 of 4 input terms covered = 50.00%
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#
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# Input Term Covered Reason for no coverage Hint
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# ----------- -------- ----------------------- --------------
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# HREADY Y
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# FinalBeatD Y
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# LSUReq N '_1' not hit Hit '_1'
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# IFUReq N No hits Hit '_0' and '_1'
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#
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# Rows: Hits FEC Target Non-masking condition(s)
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# --------- --------- -------------------- -------------------------
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# Row 1: 2 HREADY_0 ((LSUReq ~& IFUReq) && FinalBeatD)
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# Row 2: 14 HREADY_1 ((LSUReq ~& IFUReq) && FinalBeatD)
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# Row 3: 1 FinalBeatD_0 ((LSUReq ~& IFUReq) && HREADY)
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# Row 4: 14 FinalBeatD_1 ((LSUReq ~& IFUReq) && HREADY)
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# Row 5: 14 LSUReq_0 ((HREADY & FinalBeatD) && IFUReq)
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# Row 6: ***0*** LSUReq_1 ((HREADY & FinalBeatD) && IFUReq)
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# Row 7: ***0*** IFUReq_0 ((HREADY & FinalBeatD) && LSUReq)
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# Row 8: ***0*** IFUReq_1 ((HREADY & FinalBeatD) && LSUReq)
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li a0, 0x80000000
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li a1, 0x80A00000
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j label1
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.align 6 # start on multiple of 64 bytes / 16 instruction cache line
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label1:
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addi t2, t3, 0x100 # occupy part of cache line
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sfence.vma # flush tlb
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lw t0, 0x234(a0) # load to get an entry in the DTLB accessing top-level PTE
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addi t2, t3, 0x103 # occupy part of cache line
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addi t2, t3, 0x104 # occupy part of cache line
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addi t2, t3, 0x105 # occupy part of cache line
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addi t2, t3, 0x106 # occupy part of cache line
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addi t2, t3, 0x107 # occupy part of cache line
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addi t2, t3, 0x108 # occupy part of cache line
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addi t2, t3, 0x109 # occupy part of cache line
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addi t2, t3, 0x10A # occupy part of cache line
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lw t0, 0x234(a1) # trigger DTLB miss
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addi t2, t3, 0x10C # occupy part of cache line
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addi t2, t3, 0x10D # occupy part of cache line
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addi t2, t3, 0x10E # occupy part of cache line
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addi t2, t3, 0x10F # occupy part of cache line
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# next multiple of 16
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addi t2, t3, 0x100 # occupy part of cache line
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sfence.vma # flush tlb
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lw t0, 0x334(a0) # load to get an entry in the DTLB accessing top-level PTE
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addi t2, t3, 0x103 # occupy part of cache line
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addi t2, t3, 0x104 # occupy part of cache line
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addi t2, t3, 0x105 # occupy part of cache line
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addi t2, t3, 0x106 # occupy part of cache line
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addi t2, t3, 0x107 # occupy part of cache line
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addi t2, t3, 0x108 # occupy part of cache line
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addi t2, t3, 0x109 # occupy part of cache line
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addi t2, t3, 0x10A # occupy part of cache line
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addi t2, t3, 0x10B # occupy part of cache line
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lw t0, 0x334(a1) # trigger DTLB miss
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addi t2, t3, 0x10D # occupy part of cache line
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addi t2, t3, 0x10E # occupy part of cache line
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addi t2, t3, 0x10F # occupy part of cache line
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# next multiple of 16
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addi t2, t3, 0x100 # occupy part of cache line
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sfence.vma # flush tlb
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lw t0, 0x434(a0) # load to get an entry in the DTLB accessing top-level PTE
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addi t2, t3, 0x103 # occupy part of cache line
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addi t2, t3, 0x104 # occupy part of cache line
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addi t2, t3, 0x105 # occupy part of cache line
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addi t2, t3, 0x106 # occupy part of cache line
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addi t2, t3, 0x107 # occupy part of cache line
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addi t2, t3, 0x108 # occupy part of cache line
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addi t2, t3, 0x109 # occupy part of cache line
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addi t2, t3, 0x10A # occupy part of cache line
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addi t2, t3, 0x10B # occupy part of cache line
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addi t2, t3, 0x10C # occupy part of cache line
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lw t0, 0x434(a1) # trigger DTLB miss
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addi t2, t3, 0x10E # occupy part of cache line
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addi t2, t3, 0x10F # occupy part of cache line
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# next multiple of 16
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addi t2, t3, 0x100 # occupy part of cache line
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sfence.vma # flush tlb
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lw t0, 0x534(a0) # load to get an entry in the DTLB accessing top-level PTE
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addi t2, t3, 0x103 # occupy part of cache line
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addi t2, t3, 0x104 # occupy part of cache line
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addi t2, t3, 0x105 # occupy part of cache line
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addi t2, t3, 0x106 # occupy part of cache line
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addi t2, t3, 0x107 # occupy part of cache line
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addi t2, t3, 0x108 # occupy part of cache line
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addi t2, t3, 0x109 # occupy part of cache line
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addi t2, t3, 0x10A # occupy part of cache line
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addi t2, t3, 0x10B # occupy part of cache line
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addi t2, t3, 0x10C # occupy part of cache line
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addi t2, t3, 0x10D # occupy part of cache line
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lw t0, 0x534(a1) # trigger DTLB miss
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addi t2, t3, 0x10F # occupy part of cache line
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# wrap up
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li a0, 3 # switch back to machine mode because code at 0x80000000 may not have clean page table entry
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ecall
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j done
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.data
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.align 16
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# root Page table situated at 0x80010000
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pagetable:
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.8byte 0x200044C1 # 0x00000000-0x80_00000000: PTE at 0x80011000 C1 dirty, accessed, valid
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.8byte 0x00000000000010CF # misaligned terapage at 0x80_00000000
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# next page table at 0x80011000
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.align 12
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.8byte 0x00000000000010CF # misaligned gigapage at 0x00000000
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.8byte 0x00000000200058C1 # PTE for pages at 0x40000000
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.8byte 0x00000000200048C1 # gigapage at 0x80000000 pointing to 0x80120000
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# Next page table at 0x80012000 for gigapage at 0x80000000
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.align 12
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.8byte 0x0000000020004CC1 # for VA starting at 80000000 (pointer to NAPOT 64 KiB pages)
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.8byte 0x0000000020014CCF # for VA starting at 80200000 (misaligned megapage)
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.8byte 0x00000000200050C1 # for VA starting at 80400000 (bad PBMT pages)
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.8byte 0x4000000020004CC1 # for VA starting at 80600000 (bad entry: nonleaf PTE can't have PBMT != 0)
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.8byte 0x00000000200054C1 # for VA starting at 80800000 (testing rwx permissiosn with cbom/cboz)
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.8byte 0x00000000200058C1 # for VA starting at 80A00000 (pointer to NAPOT 64 KiB pages like at 80000000)
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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# Leaf page table at 0x80013000 with NAPOT pages
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.align 12
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#80000000
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.8byte 0xA0000000200020CF
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.8byte 0xA0000000200020CF
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.8byte 0xA0000000200020CF
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.8byte 0xA0000000200020CF
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.8byte 0xA0000000200020CF
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.8byte 0xA0000000200020CF
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.8byte 0xA0000000200020CF
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.8byte 0xA0000000200020CF
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.8byte 0xA0000000200020CF
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.8byte 0xA0000000200020CF
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.8byte 0xA0000000200020CF
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.8byte 0xA0000000200020CF
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.8byte 0xA0000000200020CF
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.8byte 0xA0000000200020CF
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.8byte 0xA0000000200020CF
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.8byte 0xA0000000200020CF
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.8byte 0x80000000200060CF
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.8byte 0x80000000200060CF
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.8byte 0x80000000200060CF
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.8byte 0x80000000200060CF
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.8byte 0x80000000200060CF
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.8byte 0x80000000200060CF
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.8byte 0x80000000200060CF
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.8byte 0x80000000200060CF
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.8byte 0x80000000200060CF
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.8byte 0x80000000200060CF
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.8byte 0x80000000200060CF
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.8byte 0x80000000200060CF
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.8byte 0x80000000200060CF
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.8byte 0x80000000200060CF
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.8byte 0x80000000200060CF
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.8byte 0x80000000200060CF
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.8byte 0x800000002000A0CF
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.8byte 0x800000002000A0CF
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.8byte 0x800000002000A0CF
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.8byte 0x800000002000A0CF
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.8byte 0x800000002000A0CF
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.8byte 0x800000002000A0CF
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.8byte 0x800000002000A0CF
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.8byte 0x800000002000A0CF
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.8byte 0x800000002000A0CF
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.8byte 0x800000002000A0CF
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.8byte 0x800000002000A0CF
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.8byte 0x800000002000A0CF
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.8byte 0x800000002000A0CF
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.8byte 0x800000002000A0CF
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.8byte 0x800000002000A0CF
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.8byte 0x800000002000A0CF
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.8byte 0x800000002000E0CF
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.8byte 0x800000002000E0CF
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.8byte 0x800000002000E0CF
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.8byte 0x800000002000E0CF
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.8byte 0x800000002000E0CF
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.8byte 0x800000002000E0CF
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# Leaf page table at 0x80014000 with PBMT pages
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.align 12
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#80400000
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.8byte 0x60000000200020CF # reserved entry
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# Leaf page table at 0x80015000 with various permissions for testing CBOM and CBOZ
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.align 12
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#80800000
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.8byte 0x00000000200000CF # valid rwx for VA 80800000
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.8byte 0x00000000200000CB # valid r x for VA 80801000
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.8byte 0x00000000200000C3 # valid r for VA 80802000
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.8byte 0x00000000200000C9 # valid x for VA 80803000
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.8byte 0x00000000200000CD # valid wx for VA 80804000 (illegal combination, but used to test tlbcontrol)
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.8byte 0x000000002000000F # valid rwx for VA 80805000 for covering ITLB translate and UpdateDA
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.8byte 0x20000000200000CF # PBMT=1 for VA 80806000 for covering ITLB BadPBMT
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# Leaf page table at 0x80016000 with NAPOT pages
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.align 12
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.8byte 0xA0000000200020CF
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.8byte 0xA0000000200020CF
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.8byte 0xA0000000200020CF
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.8byte 0xA0000000200020CF
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