mirror of
https://github.com/openhwgroup/cvw
synced 2025-01-31 00:44:38 +00:00
155 lines
2.3 KiB
NASM
155 lines
2.3 KiB
NASM
# start by writting the clock divider to 4 setting SDC to 25MHz
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la x3, 0x12100
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li x4, -4
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sw x4, 0x0(x3)
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# start by writting the clock divider to 1 setting SDC to 100MHZ
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la x3, 0x12100
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li x4, 1
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sw x4, 0x0(x3)
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# wait until the SDC is done with initialization
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li x4, 0x1
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wait_sdc_done_init:
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lw x5, 4(x3)
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and x5, x5, x4
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bne x5, x4, wait_sdc_done_init
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# now that it is done lets setup for a read
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li x6, 0x20000000
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sd x6, 0x10(x3) # write address register
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# send read by writting to command register
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li x7, 0x4
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sw x7, 0x8(x3)
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li x4, 0x2
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wait_sdc_done_read:
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lw x5, 4(x3)
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and x5, x5, x4
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beq x5, x4, wait_sdc_done_read
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# copy data from mailbox
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li x11, 0x80000000
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li x9, 0
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copy_sdc:
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li x8, 512/8
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ld x10, 0x18(x3) # read the mailbox
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sd x10, 0x0(x11) # write to dram
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addi x9, x9, 1
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addi x11, x11, 8
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blt x9, x8, copy_sdc
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# second read of sdc
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# now that it is done lets setup for a read
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li x6, 0x20000200
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sd x6, 0x10(x3) # write address register
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# send read by writting to command register
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li x7, 0x4
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sw x7, 0x8(x3)
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li x4, 0x2
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wait_sdc_done_read2:
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lw x5, 4(x3)
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and x5, x5, x4
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beq x5, x4, wait_sdc_done_read2
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# copy data from mailbox
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li x11, 0x80000200
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li x9, 0
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copy_sdc2:
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li x8, 512/8
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ld x10, 0x18(x3) # read the mailbox
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sd x10, 0x0(x11) # write to dram
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addi x9, x9, 1
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addi x11, x11, 8
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blt x9, x8, copy_sdc2
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# write to gpio
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li x2, 0xFF
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la x3, 0x10012000
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# +8 is output enable
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# +C is output value
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addi x4, x3, 8
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addi x5, x3, 0xC
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# write initial value of 0xFF to GPO
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sw x2, 0x0(x5)
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# enable output
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sw x2, 0x0(x4)
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# before jumping to led loop
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# lets try writting to dram.
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li x21, 0
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li x23, 4096*16 # 64KB of data
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li x22, 0x80000000
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li x24, 0
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write_loop:
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add x25, x22, x24
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sw x24, 0(x25)
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addi x24, x24, 4
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blt x24, x23, write_loop
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li x24, 0
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read_loop:
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add x25, x22, x24
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lw x21, 0(x25)
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# check value
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bne x21, x24, fail_loop
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addi x24, x24, 4
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#
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blt x24, x23, read_loop
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loop:
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# delay
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li x20, PERIOD
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delay1:
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addi x20, x20, -1
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bge x20, x0, delay1
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# new GPO
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addi x2, x2, 1
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sw x2, 0x0(x5)
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j loop
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fail_loop:
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# delay
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li x20, PERIOD/20
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fail_delay1:
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addi x20, x20, -1
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bge x20, x0, fail_delay1
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# clear GPO
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sw x0, 0x0(x5)
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# delay
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li x20, PERIOD/20
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fail_delay2:
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addi x20, x20, -1
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bge x20, x0, fail_delay2
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# write GPO
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sw x2, 0x0(x5)
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j fail_loop
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