Ross Thompson 272425c41f Added documentation about how the dcache and ptw interact.		2021-08-12 18:05:36 -05:00
..
cache	Added documentation about how the dcache and ptw interact.	2021-08-12 18:05:36 -05:00
ebu	moved subwordread to lsu	2021-07-17 20:37:20 -04:00
fpu	LZA added to FMA and attemting a merged FMA and adder in synthesis	2021-08-10 13:57:16 -04:00
generic	renamed or_rows.sv	2021-07-16 20:17:03 -04:00
hazard	Renamed DCacheStall to LSUStall in hart and hazard.	2021-07-15 10:16:16 -05:00
ieu	Moved the ReadDataW register into the datapath.	2021-07-22 14:52:03 -05:00
ifu	Fixed bug with the compressed immediate generation. Several formats should zero extend.	2021-07-26 11:55:31 -05:00
lsu	Optimized subwordread to reduce critical path from 8 muxes to 5 muxes + 1 AND gate.	2021-08-12 13:36:33 -05:00
mmu	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-07-26 11:55:00 -05:00
muldiv	Fixed disabling MulDiv when not supported. Started adding generate for FPU unsupported	2021-07-04 19:33:46 -04:00
privileged	fixed the read timer issue but we still have problems with interrupts and i/o devices.	2021-08-06 10:16:06 -05:00
uncore	Modified invalid plic reads to return 0 rather than deadbeaf.	2021-08-11 16:56:22 -05:00
wally	Moved the ReadDataW register into the datapath.	2021-07-22 14:52:03 -05:00