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slack-notifier
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Renamed regression to sim
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2023-02-02 14:48:23 -08:00 |
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wave-dos
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Renamed regression to sim
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2023-02-02 14:48:23 -08:00 |
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bpred-sim.py
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Partially working local history repair.
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2023-05-11 14:56:26 -05:00 |
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buildrootBugFinder.py
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Renamed wally-piplined.do to wally.do
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2023-02-04 04:38:41 -08:00 |
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coverage-exclusions-rv64gc.do
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Exclusions for decoders with new parameterization
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2023-05-30 01:04:39 -07:00 |
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FPbuild.txt
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Update sim-testfloat to fix errors due to bad config element. I am not sure of the reasoning, but the specific path to the testvector was not getting inserted in Questa. This modification also adds features to test individualized tests (.e.g, binary16 only) -- documentation is added in the FPbuild.txt file
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2023-06-20 17:26:54 -05:00 |
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fpga-wave.do
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Renamed regression to sim
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2023-02-02 14:48:23 -08:00 |
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GetLineNum.do
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track GetLinenum.do (tcl procedure to find line numbers to exclude)
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2023-04-12 15:58:38 -07:00 |
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imperas.ic
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add changes for latest IDV file layout
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2023-06-16 16:43:53 +01:00 |
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lint-wally
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Merge branch 'boot' into mergeBoot
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2023-07-21 17:43:45 -05:00 |
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linux-wave.do
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Modified the imperas linux scripts so they run without reporting hundreds of gigabytes of data.
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2023-04-26 17:29:57 -05:00 |
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make-tests.sh
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Renamed regression to sim
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2023-02-02 14:48:23 -08:00 |
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Makefile
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Eliminated merging non-existent coverage
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2023-05-30 00:38:30 -07:00 |
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makefile-memfile
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Renamed regression to sim
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2023-02-02 14:48:23 -08:00 |
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regression-wally
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Removed unnecessary imperas tests from coverage
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2023-05-23 15:43:11 -07:00 |
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run-imperas-linux.sh
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Revert "Update for new layout of ImperasDV files"
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2023-06-13 04:17:56 -07:00 |
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run-imperasdv-tests.bash
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Revert "Update for new layout of ImperasDV files"
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2023-06-13 04:17:56 -07:00 |
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rv64gc_CacheSim.py
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Misc typo and indent fixing.
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2023-04-13 16:54:15 -07:00 |
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sim-buildroot
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Renamed wally-piplined.do to wally.do
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2023-02-04 04:38:41 -08:00 |
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sim-buildroot-batch
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Renamed wally-piplined.do to wally.do
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2023-02-04 04:38:41 -08:00 |
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sim-imperas
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Revert "Update for new layout of ImperasDV files"
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2023-06-13 04:17:56 -07:00 |
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sim-testfloat
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Renamed regression to sim
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2023-02-02 14:48:23 -08:00 |
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sim-testfloat-batch
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For some reason this was modified - I probably made a mistake - put back vsim
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2023-06-22 15:26:22 -05:00 |
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sim-wally
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Renamed wally-piplined.do to wally.do
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2023-02-04 04:38:41 -08:00 |
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sim-wally-batch
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-06-15 15:38:38 -05:00 |
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test
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Renamed regression to sim
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2023-02-02 14:48:23 -08:00 |
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testfloat.do
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Remove path for cvw.sv so its found
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2023-06-22 15:25:56 -05:00 |
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verilate
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Changes required to make verilator compile wally's testbench to c++. Not actually tested in simulation yet.
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2023-05-31 16:51:00 -05:00 |
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wally-batch.do
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Moved cvw.sv to src root directory to avoid double-compiling and producing a warning. Adjusted to files to reflect this.
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2023-06-14 09:44:52 -07:00 |
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wally-imperas-cov.do
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add changes for latest IDV file layout
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2023-06-16 16:43:53 +01:00 |
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wally-imperas-no-idv.do
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add changes for latest IDV file layout
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2023-06-16 16:43:53 +01:00 |
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wally-imperas.do
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Removed QEMU from configurations.
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2023-07-19 10:23:55 -05:00 |
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wally-linux-imperas.do
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add changes for latest IDV file layout
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2023-06-16 16:43:53 +01:00 |
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wally.do
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Moved cvw.sv to src root directory to avoid double-compiling and producing a warning. Adjusted to files to reflect this.
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2023-06-14 09:44:52 -07:00 |
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wally.xrun
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Got xcelium running wally, but it fails to actually preload the memories.
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2023-07-12 13:56:57 -05:00 |
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wave-all.do
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Renamed regression to sim
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2023-02-02 14:48:23 -08:00 |
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wave-fpu.do
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Add reset to wave window
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2023-06-29 08:47:16 -05:00 |
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wave.do
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Removed QEMU from configurations.
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2023-07-19 10:23:55 -05:00 |
