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55 lines
2.4 KiB
Systemverilog
55 lines
2.4 KiB
Systemverilog
///////////////////////////////////////////
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// subcachelineread.sv
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//
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// Written: Ross Thompson ross1728@gmail.com
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// Created: 4 February 2022
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// Modified: 20 January 2023
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//
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// Purpose: Muxes the cache line down to the word size. Also include possible save/restore registers/muxes.
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//
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// Documentation: RISC-V System on Chip Design Chapter 7
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module subcachelineread #(parameter LINELEN, WORDLEN,
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parameter MUXINTERVAL )( // The number of bits between mux. Set to 16 for I$ to support compressed. Set to `LLEN for D$
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input logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1 : 0] PAdr, // Physical address
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input logic [LINELEN-1:0] ReadDataLine,// Read data of the whole cacheline
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output logic [WORDLEN-1:0] ReadDataWord // read data of selected word.
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);
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localparam WORDSPERLINE = LINELEN/MUXINTERVAL;
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localparam PADLEN = WORDLEN-MUXINTERVAL;
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// pad is for icache. Muxing extends over the cacheline boundary.
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logic [LINELEN+(WORDLEN-MUXINTERVAL)-1:0] ReadDataLinePad;
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logic [WORDLEN-1:0] ReadDataLineSets [(LINELEN/MUXINTERVAL)-1:0];
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if (PADLEN > 0) assign ReadDataLinePad = {{PADLEN{1'b0}}, ReadDataLine};
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else assign ReadDataLinePad = ReadDataLine;
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genvar index;
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for (index = 0; index < WORDSPERLINE; index++) begin:readdatalinesetsmux
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assign ReadDataLineSets[index] = ReadDataLinePad[(index*MUXINTERVAL)+WORDLEN-1 : (index*MUXINTERVAL)];
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end
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// variable input mux
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assign ReadDataWord = ReadDataLineSets[PAdr];
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endmodule
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