Rose Thompson d5e8ecbed5 Simplified the fpgatop SDCCLK logic.		2024-11-12 15:29:05 -06:00
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axi_sdc_controller.v	Changed SDC outputs to ensure they are aligned to the falling edge of the divided down clock rather than the processor clock.	2023-10-10 17:46:12 -05:00
fpgaTop.sv	Simplified the fpgatop SDCCLK logic.	2024-11-12 15:29:05 -06:00
fpgaTopArtyA7.sv	Updated email address authorship for my files.	2024-10-15 10:27:53 -05:00
wallypipelinedsocwrapper.sv	Updated email address authorship for my files.	2024-10-15 10:27:53 -05:00