mirror of
https://github.com/openhwgroup/cvw
synced 2025-01-23 13:04:28 +00:00
44 lines
1.7 KiB
Plaintext
44 lines
1.7 KiB
Plaintext
wally/wallypipelinedcore.sv: logic PCM
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wally/wallypipelinedcore.sv: logic TrapM
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wally/wallypipelinedcore.sv: logic InstrValidM
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wally/wallypipelinedcore.sv: logic InstrM
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lsu/lsu.sv: logic IEUAdrM
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lsu/lsu.sv: logic MemRWM
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mmu/hptw.sv: logic SATP_REGW
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uncore/uncore.sv: logic SDCCmd
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uncore/uncore.sv: logic SDCCLK
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uncore/uncore.sv: logic SDCIn
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uncore/uncore.sv: logic SDCCS
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uncore/spi_apb.sv: logic InterruptPending
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uncore/spi_apb.sv: logic TransmitFIFOWriteInc
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uncore/spi_apb.sv: logic TransmitFIFOEmpty
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uncore/spi_apb.sv: logic TransmitFIFOReadInc
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uncore/spi_apb.sv: logic TransmitLoad
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uncore/spi_apb.sv: logic ShiftEdge
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uncore/spi_apb.sv: logic SampleEdge
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uncore/spi_apb.sv: logic ReceiveShiftReg
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uncore/spi_apb.sv: logic TransmitReg
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uncore/spi_apb.sv: logic ShiftIn
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uncore/spi_apb.sv: logic EndOfFrame
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uncore/spi_apb.sv: logic TransmitRegLoaded
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uncore/spi_apb.sv: logic TransmitData
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uncore/spi_apb.sv: logic ReceiveFIFOWriteInc
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uncore/spi_apb.sv: logic ReceiveFIFOReadInc
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uncore/spi_apb.sv: logic ReceiveShiftRegEndian
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uncore/spi_apb.sv: logic ReceiveWatermark
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uncore/spi_apb.sv: logic ReceiveReadWatermarkLevel
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uncore/spi_apb.sv: logic ReceiveData
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uncore/spi_apb.sv: logic ReceiveFIFOFull
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uncore/spi_apb.sv: logic ReceiveFIFOEmpty
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uncore/spi_controller.sv: logic SCLKenable
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uncore/spi_controller.sv: statetype CurrState
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uncore/spi_controller.sv: statetype NextState
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uncore/spi_controller.sv: logic BitNum
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uncore/spi_controller.sv: logic ContinueTransmit
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uncore/spi_controller.sv: logic PhaseOneOffset
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uncore/spi_controller.sv: logic SPICLK
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uncore/spi_fifo.sv: logic rptr
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uncore/spi_fifo.sv: logic rptrnext
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uncore/spi_fifo.sv: logic raddr
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uncore/spi_fifo.sv: logic waddr
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