wally/wallypipelinedcore.sv: logic             PCM
wally/wallypipelinedcore.sv: logic    TrapM
wally/wallypipelinedcore.sv: logic                InstrValidM
wally/wallypipelinedcore.sv: logic                 InstrM
lsu/lsu.sv: logic        IEUAdrM
lsu/lsu.sv: logic       MemRWM
mmu/hptw.sv: logic	   SATP_REGW
uncore/uncore.sv: logic SDCCmd
uncore/uncore.sv: logic SDCCLK
uncore/uncore.sv: logic SDCIn
uncore/uncore.sv: logic SDCCS
uncore/spi_apb.sv: logic InterruptPending
uncore/spi_apb.sv: logic TransmitFIFOWriteInc
uncore/spi_apb.sv: logic TransmitFIFOEmpty
uncore/spi_apb.sv: logic TransmitFIFOReadInc
uncore/spi_apb.sv: logic TransmitLoad
uncore/spi_apb.sv: logic ShiftEdge
uncore/spi_apb.sv: logic SampleEdge
uncore/spi_apb.sv: logic  ReceiveShiftReg
uncore/spi_apb.sv: logic TransmitReg
uncore/spi_apb.sv: logic ShiftIn
uncore/spi_apb.sv: logic EndOfFrame
uncore/spi_apb.sv: logic TransmitRegLoaded
uncore/spi_apb.sv: logic TransmitData
uncore/spi_apb.sv: logic ReceiveFIFOWriteInc
uncore/spi_apb.sv: logic ReceiveFIFOReadInc
uncore/spi_apb.sv: logic ReceiveShiftRegEndian
uncore/spi_apb.sv: logic ReceiveWatermark
uncore/spi_apb.sv: logic ReceiveReadWatermarkLevel
uncore/spi_apb.sv: logic ReceiveData
uncore/spi_apb.sv: logic ReceiveFIFOFull
uncore/spi_apb.sv: logic ReceiveFIFOEmpty
uncore/spi_controller.sv: logic  SCLKenable
uncore/spi_controller.sv: statetype  CurrState
uncore/spi_controller.sv: statetype  NextState
uncore/spi_controller.sv: logic BitNum
uncore/spi_controller.sv: logic ContinueTransmit
uncore/spi_controller.sv: logic PhaseOneOffset
uncore/spi_controller.sv: logic SPICLK
uncore/spi_fifo.sv: logic rptr
uncore/spi_fifo.sv: logic rptrnext
uncore/spi_fifo.sv: logic raddr
uncore/spi_fifo.sv: logic waddr