Ross Thompson b8572d6a2a Changed several things. ... Removed the need to use async flip flops in SDC. Added arrs, a synchronizer for reset. I think this works with the real FPGA hardware. The last build did not include this arrs but it worked.		2021-11-12 11:13:50 -06:00
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common
fp
imperas-boottim.txt
testbench-coremark_bare.sv
testbench-coremark.sv
testbench-f64.sv
testbench-fpga.sv	Changed several things.	2021-11-12 11:13:50 -06:00
testbench-linux.sv
testbench-privileged.sv
testbench.sv
tests.vh