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169 lines
9.4 KiB
Systemverilog
169 lines
9.4 KiB
Systemverilog
///////////////////////////////////////////
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// trap.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified: dottolia@hmc.edu 14 April 2021: Add support for vectored interrupts
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//
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// Purpose: Handle Traps: Exceptions and Interrupt
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// See RISC-V Privileged Mode Specification 20190608 3.1.10-11
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module trap (
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input logic clk, reset,
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(* mark_debug = "true" *) input logic InstrMisalignedFaultM, InstrAccessFaultM, IllegalInstrFaultM,
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(* mark_debug = "true" *) input logic BreakpointFaultM, LoadMisalignedFaultM, StoreMisalignedFaultM,
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(* mark_debug = "true" *) input logic LoadAccessFaultM, StoreAccessFaultM, EcallFaultM, InstrPageFaultM,
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(* mark_debug = "true" *) input logic LoadPageFaultM, StorePageFaultM,
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(* mark_debug = "true" *) input logic mretM, sretM, uretM,
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input logic [1:0] PrivilegeModeW, NextPrivilegeModeM,
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(* mark_debug = "true" *) input logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW,
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(* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW,
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input logic STATUS_MIE, STATUS_SIE,
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input logic [`XLEN-1:0] PCM,
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input logic [`XLEN-1:0] InstrMisalignedAdrM, MemAdrM,
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input logic [31:0] InstrM,
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input logic StallW,
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input logic InstrValidM, CommittedM,
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output logic TrapM, MTrapM, STrapM, UTrapM, RetM,
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output logic InterruptM,
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output logic ExceptionM,
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output logic PendingInterruptM,
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output logic [`XLEN-1:0] PrivilegedNextPCM, CauseM, NextFaultMtvalM
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// output logic [11:0] MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW,
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// input logic WriteMIPM, WriteSIPM, WriteUIPM, WriteMIEM, WriteSIEM, WriteUIEM
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);
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logic MIntGlobalEnM, SIntGlobalEnM;
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(* mark_debug = "true" *) logic [11:0] PendingIntsM;
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//logic InterruptM;
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logic [`XLEN-1:0] PrivilegedTrapVector, PrivilegedVectoredTrapVector;
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logic Exception1M;
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// Determine pending enabled interrupts
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// interrupt if any sources are pending
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// & with a M stage valid bit to avoid interrupts from interrupt a nonexistent flushed instruction (in the M stage)
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// & with ~CommittedM to make sure MEPC isn't chosen so as to rerun the same instr twice
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assign MIntGlobalEnM = (PrivilegeModeW != `M_MODE) || STATUS_MIE; // if M ints enabled or lower priv 3.1.9
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assign SIntGlobalEnM = (PrivilegeModeW == `U_MODE) || ((PrivilegeModeW == `S_MODE) && STATUS_SIE); // if in lower priv mode, or if S ints enabled and not in higher priv mode 3.1.9
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assign PendingIntsM = ((MIP_REGW & MIE_REGW) & ({12{MIntGlobalEnM}} & 12'h888)) | ((SIP_REGW & SIE_REGW) & ({12{SIntGlobalEnM}} & 12'h222));
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assign PendingInterruptM = (|PendingIntsM) & InstrValidM;
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assign InterruptM = PendingInterruptM & ~CommittedM;
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//assign ExceptionM = TrapM;
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assign ExceptionM = Exception1M;
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// *** as of 7/17/21, the system passes with this definition of ExceptionM as being all traps and fails if ExceptionM = Exception1M
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// with no interrupts. However, Ross intended the datacache to use Exception without interrupts, so there is something subtle
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// to sort out here.
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// *** as of 8/13/21, switching to Exception1M does not seem to cause any failures. It's possible the bug was
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// fixed inadvertantly as the dcache was debugged.
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// Trigger Traps and RET
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// According to RISC-V Spec Section 1.6, exceptions are caused by instructions. Interrupts are external asynchronous.
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// Traps are the union of exceptions and interrupts.
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assign Exception1M = InstrMisalignedFaultM | InstrAccessFaultM | IllegalInstrFaultM |
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LoadMisalignedFaultM | StoreMisalignedFaultM |
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InstrPageFaultM | LoadPageFaultM | StorePageFaultM |
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BreakpointFaultM | EcallFaultM |
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LoadAccessFaultM | StoreAccessFaultM;
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assign TrapM = Exception1M | InterruptM; // *** clean this up later DH
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assign MTrapM = TrapM & (NextPrivilegeModeM == `M_MODE);
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assign STrapM = TrapM & (NextPrivilegeModeM == `S_MODE) & `S_SUPPORTED;
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assign UTrapM = TrapM & (NextPrivilegeModeM == `U_MODE) & `N_SUPPORTED;
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assign RetM = mretM | sretM | uretM;
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always_comb
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if (NextPrivilegeModeM == `U_MODE) PrivilegedTrapVector = UTVEC_REGW;
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else if (NextPrivilegeModeM == `S_MODE) PrivilegedTrapVector = STVEC_REGW;
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else PrivilegedTrapVector = MTVEC_REGW;
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// Handle vectored traps (when mtvec/stvec/utvec csr value has bits [1:0] == 01)
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// For vectored traps, set program counter to _tvec value + 4 times the cause code
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//
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// POSSIBLE OPTIMIZATION:
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// From 20190608 privielegd spec page 27 (3.1.7)
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// > Allowing coarser alignments in Vectored mode enables vectoring to be
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// > implemented without a hardware adder circuit.
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// For example, we could require m/stvec be aligned on 7 bits to let us replace the adder directly below with
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// [untested] PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:7], CauseM[3:0], 4'b0000}
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generate
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if(`VECTORED_INTERRUPTS_SUPPORTED) begin
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always_comb
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if (PrivilegedTrapVector[1:0] == 2'b01 && CauseM[`XLEN-1] == 1)
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PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2] + {CauseM[`XLEN-5:0], 2'b00}, 2'b00};
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else
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PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2], 2'b00};
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end
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else begin
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assign PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2], 2'b00};
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end
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endgenerate
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always_comb
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if (mretM) PrivilegedNextPCM = MEPC_REGW;
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else if (sretM) PrivilegedNextPCM = SEPC_REGW;
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else if (uretM) PrivilegedNextPCM = UEPC_REGW;
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else PrivilegedNextPCM = PrivilegedVectoredTrapVector;
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// Cause priority defined in table 3.7 of 20190608 privileged spec
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// Exceptions are of lower priority than all interrupts (3.1.9)
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always_comb
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if (reset) CauseM = 0; // hard reset 3.3
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else if (PendingIntsM[11]) CauseM = (1 << (`XLEN-1)) + 11; // Machine External Int
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else if (PendingIntsM[3]) CauseM = (1 << (`XLEN-1)) + 3; // Machine Sw Int
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else if (PendingIntsM[7]) CauseM = (1 << (`XLEN-1)) + 7; // Machine Timer Int
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else if (PendingIntsM[9]) CauseM = (1 << (`XLEN-1)) + 9; // Supervisor External Int
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else if (PendingIntsM[1]) CauseM = (1 << (`XLEN-1)) + 1; // Supervisor Sw Int
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else if (PendingIntsM[5]) CauseM = (1 << (`XLEN-1)) + 5; // Supervisor Timer Int
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else if (InstrPageFaultM) CauseM = 12;
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else if (InstrAccessFaultM) CauseM = 1;
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else if (InstrMisalignedFaultM) CauseM = 0;
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else if (IllegalInstrFaultM) CauseM = 2;
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else if (BreakpointFaultM) CauseM = 3;
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else if (EcallFaultM) CauseM = {{(`XLEN-2){1'b0}}, PrivilegeModeW} + 8;
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else if (LoadMisalignedFaultM) CauseM = 4;
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else if (StoreMisalignedFaultM) CauseM = 6;
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else if (LoadPageFaultM) CauseM = 13;
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else if (StorePageFaultM) CauseM = 15;
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else if (LoadAccessFaultM) CauseM = 5;
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else if (StoreAccessFaultM) CauseM = 7;
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else CauseM = 0;
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// MTVAL
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// 3.1.17: on instruction fetch, load, or store address misaligned access or page fault
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// mtval is written with the faulting virtual address.
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// On illegal instruction trap, mtval may be written with faulting instruction
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// For other traps (including interrupts), mtval is set to 0
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// *** hardware breakpoint is supposed to write faulting virtual address per priv p. 38
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// *** Page faults not yet implemented
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// Technically
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always_comb
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if (InstrMisalignedFaultM) NextFaultMtvalM = InstrMisalignedAdrM;
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else if (LoadMisalignedFaultM) NextFaultMtvalM = MemAdrM;
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else if (StoreMisalignedFaultM) NextFaultMtvalM = MemAdrM;
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else if (BreakpointFaultM) NextFaultMtvalM = PCM;
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else if (InstrPageFaultM) NextFaultMtvalM = PCM;
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else if (LoadPageFaultM) NextFaultMtvalM = MemAdrM;
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else if (StorePageFaultM) NextFaultMtvalM = MemAdrM;
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else if (IllegalInstrFaultM) NextFaultMtvalM = {{(`XLEN-32){1'b0}}, InstrM};
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else NextFaultMtvalM = 0;
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endmodule
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