bbracker 5022647041 Revert "first attempt at verilog side of checkpoint functionality" ... This reverts commit f6ef8e5656.		2021-09-30 20:45:26 -04:00
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csr.sv	Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.	2021-09-15 13:14:00 -04:00
csrc.sv	Revert "first attempt at verilog side of checkpoint functionality"	2021-09-30 20:45:26 -04:00
csri.sv	Revert "first attempt at verilog side of checkpoint functionality"	2021-09-30 20:45:26 -04:00
csrm.sv	Revert "first attempt at verilog side of checkpoint functionality"	2021-09-30 20:45:26 -04:00
csrn.sv	Gave names to for loops in generate blocks for ease of reference	2021-07-04 18:52:16 -04:00
csrs.sv	Revert "first attempt at verilog side of checkpoint functionality"	2021-09-30 20:45:26 -04:00
csrsr.sv	Revert "first attempt at verilog side of checkpoint functionality"	2021-09-30 20:45:26 -04:00
csru.sv	Fixed writting MStatus FS bits	2021-07-13 13:20:30 -04:00
privdec.sv	Implemented TSR, TW, TVM, MXR status bits	2021-07-06 01:32:05 -04:00
privileged.sv	Modified the preformance counter's InstRet to include ECALL and EBREAK by changing the hazard logic so these instructions don't self flush the W stage.	2021-08-23 15:46:17 -05:00
trap.sv	Fixed MTVAL contents during breakpoint. Now all riscv-arch-test vectors pass in rv32 and rv64	2021-09-13 12:40:40 -04:00