mirror of
https://github.com/openhwgroup/cvw
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78 lines
3.0 KiB
Systemverilog
78 lines
3.0 KiB
Systemverilog
///////////////////////////////////////////
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// uart_apb.sv
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//
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// Written: David_Harris@hmc.edu 21 January 2021
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// Modified:
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//
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// Purpose: APB Interface to Universial Asynchronous Receiver/ Transmitter with FIFOs
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// Emulates interface of Texas Instruments PC165550D
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// Compatible with UART in Imperas Virtio model
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//
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// Documentation: RISC-V System on Chip Design
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module uart_apb import cvw::*; #(parameter cvw_t P) (
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input logic PCLK, PRESETn,
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input logic PSEL,
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input logic [2:0] PADDR,
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input logic [P.XLEN-1:0] PWDATA,
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input logic [P.XLEN/8-1:0] PSTRB,
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input logic PWRITE,
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input logic PENABLE,
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output logic [P.XLEN-1:0] PRDATA,
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output logic PREADY,
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input logic SIN, DSRb, DCDb, CTSb, RIb, // from E1A driver from RS232 interface
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output logic SOUT, RTSb, DTRb, // to E1A driver to RS232 interface
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output logic OUT1b, OUT2b, INTR, TXRDYb, RXRDYb); // to CPU
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// UART interface signals
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logic [2:0] entry;
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logic MEMRb, MEMWb, memread, memwrite;
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logic [7:0] Din, Dout;
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assign memwrite = PWRITE & PENABLE & PSEL; // only write in access phase
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assign memread = ~PWRITE & PENABLE & PSEL;
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assign PREADY = 1'b1; // CLINT never takes >1 cycle to respond
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assign entry = PADDR[2:0];
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assign MEMRb = ~memread;
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assign MEMWb = ~memwrite;
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assign Din = PWDATA[7:0];
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if (P.XLEN == 64) assign PRDATA = {Dout, Dout, Dout, Dout, Dout, Dout, Dout, Dout};
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else assign PRDATA = {Dout, Dout, Dout, Dout};
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logic BAUDOUTb; // loop tx clock BAUDOUTb back to rx clock RCLK
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uartPC16550D #(P.UART_PRESCALE) uartPC(
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// Processor Interface
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.PCLK, .PRESETn,
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.A(entry), .Din,
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.Dout,
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.MEMRb, .MEMWb,
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.INTR, .TXRDYb, .RXRDYb,
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// Clocks
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.BAUDOUTb, .RCLK(BAUDOUTb),
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// E1A Driver
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.SIN, .DSRb, .DCDb, .CTSb, .RIb,
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.SOUT, .RTSb, .DTRb, .OUT1b, .OUT2b
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);
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endmodule
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