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47 lines
2.0 KiB
Systemverilog
Executable File
47 lines
2.0 KiB
Systemverilog
Executable File
// This module takes as inputs two operands (op1 and op2)
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// and the result precision (P). Based on the operation and precision,
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// it conditionally converts single precision values to double
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// precision values and modifies the sign of op1.
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// The converted operands are Float1 and Float2.
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module convert_inputs_div (
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input logic [63:0] op1, // 1st input operand (A)
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input logic [63:0] op2, // 2nd input operand (B)
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input logic P, // Result Precision (0 for double, 1 for single)
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input logic op_type, // Operation
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output logic [63:0] Float1, // Converted 1st input operand
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output logic [63:0] Float2b // Converted 2nd input operand
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);
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logic [63:0] Float2;
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logic Zexp1; // One if the exponent of op1 is zero
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logic Zexp2; // One if the exponent of op2 is zero
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logic Oexp1; // One if the exponent of op1 is all ones
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logic Oexp2; // One if the exponent of op2 is all ones
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// Test if the input exponent is zero, because if it is then the
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// exponent of the converted number should be zero.
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assign Zexp1 = ~(|op1[30:23]);
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assign Zexp2 = ~(|op2[30:23]);
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assign Oexp1 = (&op1[30:23]);
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assign Oexp2 = (&op2[30:23]);
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// Conditionally convert op1. Lower 29 bits are zero for single precision.
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assign Float1[62:29] = P ? {op1[30], {3{(~op1[30]&~Zexp1)|Oexp1}}, op1[29:0]}
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: op1[62:29];
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assign Float1[28:0] = op1[28:0] & {29{~P}};
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// Conditionally convert op2. Lower 29 bits are zero for single precision.
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assign Float2[62:29] = P ? {op2[30], {3{(~op2[30]&~Zexp2)|Oexp2}}, op2[29:0]}
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: op2[62:29];
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assign Float2[28:0] = op2[28:0] & {29{~P}};
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// Set the sign of Float1 based on its original sign
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assign Float1[63] = P ? op1[31] : op1[63];
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assign Float2[63] = P ? op2[31] : op2[63];
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// For sqrt, assign Float2 same as Float1 for simplicity
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assign Float2b = op_type ? Float1 : Float2;
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endmodule // convert_inputs
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