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31 lines
1.1 KiB
Markdown
31 lines
1.1 KiB
Markdown
# core-v-wally Design Verification Test Plan
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This document outlines the test plan for the Wally rv64gc configuration to reach Technology Readiness Level 5.
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1. Pass riscv-arch-test
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2. Boot Linux
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3. FPU pass all TestFloat vectors
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4. Performance verification: Caches and branch predictor miss rates match independent simulation
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5. Directed tests
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- Privileged unit: Chapter 5 test plan
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- MMU: PMA, PMP, virtual memory: Chapter 8 test plan
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- Peripherals: Chapter 16 test plan
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6. Random tests
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- riscdv tests
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7. Coverage tests
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- Directed tests to bring coverage up to 100%.
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- Statement, experssion, branch, condition, FSM coverage in Questa
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- Do not measure toggle coverage
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All tests operate correctly in lock-step with ImperasDV
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Open questions:
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1. How to define extent of riscdv random tests needed?
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2. What other directed tests?
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PMP Tests
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Virtual Memory Tests
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How to define pipeline tests?
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Simple ones like use after load stall are not important.
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Hard ones such as page table walker fault during data access while I$ access is pending are hard to articulate and code
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Is there an example of a good directed pipeline test plan & implementation
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