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https://github.com/openhwgroup/cvw
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89 lines
4.2 KiB
Systemverilog
89 lines
4.2 KiB
Systemverilog
///////////////////////////////////////////
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// mdu.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: M extension multiply and divide
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//
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// Documentation: RISC-V System on Chip Design
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module mdu import cvw::*; #(parameter cvw_t P) (
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input logic clk, reset,
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input logic StallM, StallW,
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input logic FlushE, FlushM, FlushW,
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input logic [P.XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // inputs A and B from IEU forwarding mux output
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input logic [2:0] Funct3E, Funct3M, // type of MDU operation
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input logic IntDivE, W64E, // Integer division/remainder, and W-type instrutions
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input logic MDUActiveE, // Mul/Div instruction being executed
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output logic [P.XLEN-1:0] MDUResultW, // multiply/divide result
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output logic DivBusyE // busy signal to stall pipeline in Execute stage
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);
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logic [P.XLEN*2-1:0] ProdM; // double-width product from mul
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logic [P.XLEN-1:0] QuotM, RemM; // quotient and remainder from intdivrestoring
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logic [P.XLEN-1:0] PrelimResultM; // selected result before W truncation
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logic [P.XLEN-1:0] MDUResultM; // result after W truncation
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logic W64M; // W-type instruction
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// Multiplier
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mul #(P.XLEN) mul(.clk, .reset, .StallM, .FlushM, .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .ProdM);
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// Divider
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// Start a divide when a new division instruction is received and the divider isn't already busy or finishing
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// When IDIV_ON_FPU is set, use the FPU divider instead
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// In ZMMUL, with M_SUPPORTED = 0, omit the divider
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if ((P.IDIV_ON_FPU & P.F_SUPPORTED) | (!P.M_SUPPORTED)) begin:nodiv
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assign QuotM = '0;
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assign RemM = '0;
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assign DivBusyE = 1'b0;
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end else begin:div
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div #(P) div(.clk, .reset, .StallM, .FlushE, .DivSignedE(~Funct3E[0]), .W64E, .IntDivE,
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.ForwardedSrcAE, .ForwardedSrcBE, .DivBusyE, .QuotM, .RemM);
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end
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// Result multiplexer
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// For ZMMUL, QuotM and RemM are tied to 0, so the mux automatically simplifies
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always_comb
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case (Funct3M)
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3'b000: PrelimResultM = ProdM[P.XLEN-1:0]; // mul
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3'b001: PrelimResultM = ProdM[P.XLEN*2-1:P.XLEN]; // mulh
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3'b010: PrelimResultM = ProdM[P.XLEN*2-1:P.XLEN]; // mulhsu
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3'b011: PrelimResultM = ProdM[P.XLEN*2-1:P.XLEN]; // mulhu
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3'b100: PrelimResultM = QuotM; // div
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3'b101: PrelimResultM = QuotM; // divu
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3'b110: PrelimResultM = RemM; // rem
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3'b111: PrelimResultM = RemM; // remu
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endcase
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// Handle sign extension for W-type instructions
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flopenrc #(1) W64MReg(clk, reset, FlushM, ~StallM, W64E, W64M);
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if (P.XLEN == 64) begin:resmux // RV64 has W-type instructions
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assign MDUResultM = W64M ? {{32{PrelimResultM[31]}}, PrelimResultM[31:0]} : PrelimResultM;
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end else begin:resmux // RV32 has no W-type instructions
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assign MDUResultM = PrelimResultM;
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end
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// Writeback stage pipeline register
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flopenrc #(P.XLEN) MDUResultWReg(clk, reset, FlushW, ~StallW, MDUResultM, MDUResultW);
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endmodule // mdu
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