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51 lines
1.8 KiB
Systemverilog
51 lines
1.8 KiB
Systemverilog
///////////////////////////////////////////
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// vm64check.sv
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//
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// Written: David_Harris@hmc.edu 4 November 2022
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// Modified:
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//
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// Purpose: Check for good upper address bits in RV64 mode
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//
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// Documentation: RISC-V System on Chip Design Chapter 8
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module vm64check (
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input logic [`SVMODE_BITS-1:0] SATP_MODE,
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input logic [`XLEN-1:0] VAdr,
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output logic SV39Mode,
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output logic UpperBitsUnequalPageFault
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);
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if (`XLEN == 64) begin
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assign SV39Mode = (SATP_MODE == `SV39);
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// page fault if upper bits aren't all the same
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logic eq_63_47, eq_46_38;
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assign eq_46_38 = &(VAdr[46:38]) | ~|(VAdr[46:38]);
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assign eq_63_47 = &(VAdr[63:47]) | ~|(VAdr[63:47]);
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assign UpperBitsUnequalPageFault = SV39Mode ? ~(eq_63_47 & eq_46_38) : ~eq_63_47;
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end else begin
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assign SV39Mode = 0;
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assign UpperBitsUnequalPageFault = 0;
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end
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endmodule
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