Ross Thompson 0ed0c18aa1 Fixed a very subtle bug in the trap handler. It was possible to select the wrong cause if an interrupt was pending, but it was supressed by Committed and another exception triggered.		2022-10-02 16:21:21 -05:00
..
csr.sv	Cause simplification	2022-05-12 23:47:21 +00:00
csrc.sv	Clean up unused signals	2022-05-12 14:49:58 +00:00
csri.sv	Removed more unused signals, simplified csri state	2022-05-12 15:10:10 +00:00
csrm.sv	Fixed typo in csrm	2022-05-12 06:55:39 -07:00
csrs.sv	Updated fpga debugger.	2022-05-17 23:04:01 -05:00
csrsr.sv	Preliminary support for big endian modes. Regression passes but no big endian tests written yet.	2022-05-08 06:46:35 +00:00
csru.sv	Illegal instruction fault when running FPU instruction with STATUS_FS = 0	2022-05-03 18:32:01 +00:00
privdec.sv	Cleaned up fcvt selection control to IEU and FPUIllegalInst signals	2022-08-23 12:17:19 -07:00
privileged.sv	Hmm. the icache and ifu didn't have a CommittedF signals going back to the privileged unit. They probably should. If an interrupt occurred during the middle of an instruction fetch icache miss I think it would corrupt the icache.	2022-09-28 17:39:51 -05:00
privmode.sv	../src/privileged/csrc.sv	2022-05-31 21:12:17 +00:00
privpiperegs.sv	Cleaned up fcvt selection control to IEU and FPUIllegalInst signals	2022-08-23 12:17:19 -07:00
trap.sv	Fixed a very subtle bug in the trap handler. It was possible to select the wrong cause if an interrupt was pending, but it was supressed by Committed and another exception triggered.	2022-10-02 16:21:21 -05:00