Skylar Litz 29d1f64588 add AtemptedInstructionCount signal		2022-03-26 21:28:57 +00:00
..
slack-notifier
wave-dos
wkdir
buildrootBugFinder.py	update to match new filesystem organization	2022-03-26 21:28:32 +00:00
fpga-wave.do
lint-wally
linux-wave.do	add AtemptedInstructionCount signal	2022-03-26 21:28:57 +00:00
make-tests.sh
Makefile	Fixed fma files to stop breaking synthesis. Changed Makefiles to skip Imperas	2022-03-03 15:38:08 +00:00
makefile-memfile	Fixed fma files to stop breaking synthesis. Changed Makefiles to skip Imperas	2022-03-03 15:38:08 +00:00
regression-wally	remove imperas32p tests	2022-03-04 00:06:18 +00:00
sim-buildroot	switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv	2022-03-01 03:11:43 +00:00
sim-buildroot-batch	switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv	2022-03-01 03:11:43 +00:00
sim-coremark-batch	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
sim-fp64
sim-fp64-batch	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
sim-wally
sim-wally-batch	Merged TIM and regular testbenches. RV32e now working and back in regression.	2022-02-08 12:18:13 +00:00
wally-coremark.do	Improve wavefile by adding performance counters.	2022-01-12 10:53:29 -06:00
wally-fp64-batch.do	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
wally-fp64.do
wally-harvard.do
wally-pipelined-batch.do	switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv	2022-03-01 03:11:43 +00:00
wally-pipelined-fpga.do	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
wally-pipelined.do	buildroot graphical sim bugfix	2022-03-01 03:24:23 +00:00
wave-all.do	Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.	2022-01-27 17:11:27 -06:00
wave-coremark.do
wave.do	add CSRs to waveview	2022-03-02 18:31:10 +00:00