Rose Thompson 24609f0b7f Now have configurations to switch between supporting RVVI over ethernet.		2024-07-22 10:51:13 -05:00
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rv32e	Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes.	2024-07-19 17:08:47 -05:00
rv32gc	Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes.	2024-07-19 17:08:47 -05:00
rv32i	Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes.	2024-07-19 17:08:47 -05:00
rv32imc	Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes.	2024-07-19 17:08:47 -05:00
rv64gc	Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes.	2024-07-19 17:08:47 -05:00
rv64i	Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes.	2024-07-19 17:08:47 -05:00
shared	Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes.	2024-07-19 17:08:47 -05:00
derivlist.txt	Now have configurations to switch between supporting RVVI over ethernet.	2024-07-22 10:51:13 -05:00