Ross Thompson 89a7b38f79 Removed 1 cycle delay on store miss. ... Changed some logic to partially support atomics.		2021-07-30 14:00:51 -05:00
..
cache	Removed 1 cycle delay on store miss.	2021-07-30 14:00:51 -05:00
ebu	moved subwordread to lsu	2021-07-17 20:37:20 -04:00
fpu	fixed some fpu lint errors	2021-07-24 16:41:12 -04:00
generic	renamed or_rows.sv	2021-07-16 20:17:03 -04:00
hazard	Renamed DCacheStall to LSUStall in hart and hazard.	2021-07-15 10:16:16 -05:00
ieu	Moved the ReadDataW register into the datapath.	2021-07-22 14:52:03 -05:00
ifu	Fixed bug with the compressed immediate generation. Several formats should zero extend.	2021-07-26 11:55:31 -05:00
lsu	Added additional interlock for itlb miss -> instrPageFault with concurrent memory operation.	2021-07-25 23:14:28 -05:00
mmu	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-07-26 11:55:00 -05:00
muldiv	Fixed disabling MulDiv when not supported. Started adding generate for FPU unsupported	2021-07-04 19:33:46 -04:00
privileged	fixed issue with tlbflush remaining high during a stalled sfence instruction	2021-07-21 17:43:36 -04:00
uncore	fix UART RX FIFO bug where tail pointer can overtake head pointer	2021-07-22 02:09:41 -04:00
wally	Moved the ReadDataW register into the datapath.	2021-07-22 14:52:03 -05:00