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78 lines
3.1 KiB
Systemverilog
78 lines
3.1 KiB
Systemverilog
///////////////////////////////////////////
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// amoalu.sv
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//
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// Written: David_Harris@hmc.edu
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// Created: 10 March 2021
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// Modified: 18 January 2023
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//
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// Purpose: Performs AMO operations
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//
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// Documentation: RISC-V System on Chip Design Chapter 14 (Figure ***)
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module amoalu (
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input logic [`XLEN-1:0] ReadDataM, // LSU's ReadData
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input logic [`XLEN-1:0] IHWriteDataM, // LSU's WriteData
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input logic [6:0] LSUFunct7M, // ALU Operation
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input logic [2:0] LSUFunct3M, // Memoy access width
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output logic [`XLEN-1:0] AMOResult // ALU output
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);
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logic [`XLEN-1:0] a, b, y;
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// *** see how synthesis generates this and optimize more structurally if necessary to share hardware
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// a single carry chain should be shared for + and the four min/max
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// and the same mux can be used to select b for swap.
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always_comb
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case (LSUFunct7M[6:2])
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5'b00001: y = b; // amoswap
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5'b00000: y = a + b; // amoadd
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5'b00100: y = a ^ b; // amoxor
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5'b01100: y = a & b; // amoand
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5'b01000: y = a | b; // amoor
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5'b10000: y = ($signed(a) < $signed(b)) ? a : b; // amomin
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5'b10100: y = ($signed(a) >= $signed(b)) ? a : b; // amomax
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5'b11000: y = ($unsigned(a) < $unsigned(b)) ? a : b; // amominu
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5'b11100: y = ($unsigned(a) >= $unsigned(b)) ? a : b; // amomaxu
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default: y = `XLEN'bx; // undefined; *** could change to b for efficiency
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endcase
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// sign extend if necessary
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if (`XLEN == 32) begin:sext
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assign a = ReadDataM;
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assign b = IHWriteDataM;
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assign AMOResult = y;
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end else begin:sext // `XLEN = 64
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always_comb
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if (LSUFunct3M[1:0] == 2'b10) begin // sign-extend word-length operations
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a = {{32{ReadDataM[31]}}, ReadDataM[31:0]};
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b = {{32{IHWriteDataM[31]}}, IHWriteDataM[31:0]};
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AMOResult = {{32{y[31]}}, y[31:0]};
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end else begin
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a = ReadDataM;
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b = IHWriteDataM;
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AMOResult = y;
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end
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end
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endmodule
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