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123 lines
5.6 KiB
Systemverilog
123 lines
5.6 KiB
Systemverilog
///////////////////////////////////////////
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// ebufsmarb
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//
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// Written: Ross Thompson ross1728@gmail.com
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// Created: 23 January 2023
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// Modified: 23 January 2023
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//
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// Purpose: Arbitrates requests from instruction and data streams
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// LSU has priority.
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//
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// Documentation: RISC-V System on Chip Design Chapter 6 (Figures 6.25 and 6.26)
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module ebufsmarb (
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input logic HCLK,
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input logic HRESETn,
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input logic [2:0] HBURST,
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// AHB burst length
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input logic HREADY,
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input logic LSUReq,
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input logic IFUReq,
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output logic IFUSave,
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output logic IFURestore,
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output logic IFUDisable,
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output logic IFUSelect,
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output logic LSUDisable,
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output logic LSUSelect);
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typedef enum logic [1:0] {IDLE, ARBITRATE} statetype;
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statetype CurrState, NextState;
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logic both; // Both the LSU and IFU request at the same time
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logic IFUReqD; // 1 cycle delayed IFU request. Part of arbitration
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logic FinalBeat, FinalBeatD; // Indicates the last beat of a burst
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logic BeatCntEn;
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logic [3:0] BeatCount; // Position within a burst transfer
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logic BeatCntReset;
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logic [3:0] Threshold; // Number of beats derived from HBURST
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// Aribtration scheme
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// FSM decides if arbitration needed. Arbitration is held until the last beat of
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// a burst is completed.
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////////////////////////////////////////////////////////////////////////////////////////////////////
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assign both = LSUReq & IFUReq;
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flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextState, IDLE, CurrState);
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always_comb
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case (CurrState)
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IDLE: if (both) NextState = ARBITRATE;
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else NextState = IDLE;
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ARBITRATE: if (HREADY & FinalBeatD & ~(LSUReq & IFUReq)) NextState = IDLE;
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else NextState = ARBITRATE;
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default: NextState = IDLE;
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endcase
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// basic arb always selects LSU when both
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// replace this block for more sophisticated arbitration as needed.
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// Controller 0 (IFU)
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assign IFUSave = CurrState == IDLE & both;
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assign IFURestore = CurrState == ARBITRATE;
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assign IFUDisable = CurrState == ARBITRATE;
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assign IFUSelect = (NextState == ARBITRATE) ? 1'b0 : IFUReq;
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// Controller 1 (LSU)
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// When both the IFU and LSU request at the same time, the FSM will go into the arbitrate state.
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// Once the LSU request is done the fsm returns to IDLE. To prevent the LSU from regaining
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// priority and re issuing the same memroy operation, the delayed IFUReqD squashes the LSU request.
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// This is necessary because the pipeline is stalled for the entire duration of both transactions,
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// and the LSU memory request will stil be active.
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flopr #(1) ifureqreg(HCLK, ~HRESETn, IFUReq, IFUReqD);
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assign LSUDisable = (CurrState == ARBITRATE) ? 1'b0 : (IFUReqD & ~(HREADY & FinalBeatD));
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assign LSUSelect = (NextState == ARBITRATE) ? 1'b1: LSUReq;
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// Burst mode logic
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////////////////////////////////////////////////////////////////////////////////////////////////////
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assign BeatCntReset = NextState == IDLE;
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assign FinalBeat = (BeatCount == Threshold); // Detect when we are waiting on the final access.
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// Counting the beats in the EBU is only necessary when both the LSU and IFU request concurrently.
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// LSU has priority. HREADY serves double duty during a burst transaction. It indicates when the
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// beat completes and when the transaction finishes. However there is nothing external to
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// differentiate them. The EBU counts the HREADY beats so it knows when to switch to the IFU's
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// request.
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assign BeatCntEn = (NextState == ARBITRATE) & HREADY;
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counter #(4) BeatCounter(HCLK, ~HRESETn | BeatCntReset | FinalBeat, BeatCntEn, BeatCount);
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// Used to store data from data phase of AHB.
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flopenr #(1) FinalBeatReg(HCLK, ~HRESETn | BeatCntReset, BeatCntEn, FinalBeat, FinalBeatD);
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// unlike the bus fsm in lsu/ifu, we need to derive the number of beats from HBURST, Threshold = num beats - 1.
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// HBURST[2:1] Beats threshold
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// 00 1 0
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// 01 4 3
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// 10 8 7
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// 11 16 15
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always_comb
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if (HBURST[2:1] == 2'b00) Threshold = 4'b0000;
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else Threshold = (2 << HBURST[2:1]) - 1;
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endmodule
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