bbracker 17960a6484 Ah big ole merge! Passes sim-wally-batch and linting, so should be fine		2021-06-08 12:41:25 -04:00
..
csr.sv	Second attept to commit refactoring config files	2021-06-07 12:37:46 -04:00
csrc.sv	Second attept to commit refactoring config files	2021-06-07 12:37:46 -04:00
csri.sv	Merge branch 'tests' into icache-almost-working	2021-04-25 21:25:36 -05:00
csrm.sv	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-05-03 23:15:39 -04:00
csrn.sv	Fix bug that caused stvec to get the wrong value	2021-05-03 17:54:57 -04:00
csrs.sv	Fix bug that caused stvec to get the wrong value	2021-05-03 17:54:57 -04:00
csrsr.sv	Second attept to commit refactoring config files	2021-06-07 12:37:46 -04:00
csru.sv	FMV.D.X imperas test passes	2021-05-20 22:17:59 -04:00
privdec.sv	Second attept to commit refactoring config files	2021-06-07 12:37:46 -04:00
privileged.sv	Ah big ole merge! Passes sim-wally-batch and linting, so should be fine	2021-06-08 12:41:25 -04:00
trap.sv	* GPIO comprehensive testing	2021-06-08 12:32:46 -04:00