cvw/pipelined/src
2022-07-21 01:20:06 +00:00
..
cache Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-12 22:37:20 +00:00
ebu Moved HWSTRB to ahblite, factored out of peripherals. Moved old AHB peripherals to unusedsrc 2022-07-08 09:09:02 +00:00
fpu added input enables and improved forwarding 2022-07-21 01:20:06 +00:00
generic removed warnings and took a mux out of the critical path 2022-07-12 18:32:17 -07:00
hazard srt divider merged into fpu 2022-07-07 16:01:33 -07:00
ieu added rv32 double precision stores - untested 2022-06-28 21:33:31 +00:00
ifu renamed FLoad2 to FStore2 2022-07-09 00:26:45 +00:00
lsu found the bug in the store modification 2022-07-12 22:42:19 +00:00
mmu took first match out of pmpadrdec 2022-07-06 00:02:01 +00:00
muldiv Clean up unused signals 2022-05-12 14:49:58 +00:00
ppa cleanup, plots for paper 2022-06-15 18:28:36 +00:00
privileged Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working. 2022-06-02 14:18:55 +00:00
uncore restored intPending logic to be sticky for PLIC 2022-07-16 17:43:31 -07:00
wally Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-12 22:37:20 +00:00
sdc piplined directory cleanup 2022-01-07 12:43:50 +00:00