bbracker 41b3912abc buildroot graphical sim bugfix		2022-03-01 03:24:23 +00:00
..
slack-notifier
wave-dos
wkdir	Moved regression work directories to regression/wkdir to reduce clutter	2022-02-27 17:35:09 +00:00
buildrootBugFinder.py	update bugfinder script to new file organization	2022-02-15 22:58:18 +00:00
fpga-wave.do	More cache cleanup.	2022-02-13 15:47:27 -06:00
lint-wally
linux-wave.do	Accidentally cleared dirty bit when setting access bit in hptw.	2022-02-17 16:20:20 -06:00
make-tests.sh
Makefile	Temporarily removed tests/imperas-riscv-tests from Makefile because of license issue	2022-02-27 15:12:10 +00:00
makefile-memfile
regression-wally	switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv	2022-03-01 03:11:43 +00:00
sim-buildroot	switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv	2022-03-01 03:11:43 +00:00
sim-buildroot-batch	switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv	2022-03-01 03:11:43 +00:00
sim-coremark-batch
sim-fp64
sim-fp64-batch
sim-wally
sim-wally-batch	Merged TIM and regular testbenches. RV32e now working and back in regression.	2022-02-08 12:18:13 +00:00
wally-coremark.do
wally-fp64-batch.do
wally-fp64.do
wally-harvard.do
wally-pipelined-batch.do	switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv	2022-03-01 03:11:43 +00:00
wally-pipelined-fpga.do
wally-pipelined.do	buildroot graphical sim bugfix	2022-03-01 03:24:23 +00:00
wave-all.do
wave-coremark.do	More cache cleanup.	2022-02-13 15:47:27 -06:00
wave.do	change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests	2022-02-22 03:46:08 +00:00