Rose Thompson 510e3a268c Added spi debugger to build script.		2024-09-05 12:04:14 -07:00
..
debug	Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile.	2022-10-24 15:38:39 -05:00
ahbaxibridge.tcl	More updates to fpga IP module names.	2024-08-22 14:31:39 -07:00
bootrom.txt	Added bootrom.txt.	2022-03-30 17:29:48 -05:00
clkconverter.tcl	More updates to fpga IP module names.	2024-08-22 14:31:39 -07:00
ddr3-ArtyA7.tcl	More updates to fpga IP module names.	2024-08-22 14:31:39 -07:00
ddr4-vcu108.tcl	This actually fixes the vcu108 to correctly set the SPI clock frequency.	2024-09-03 13:11:03 -07:00
ddr4-vcu118.tcl	Fixed bugs in the fpga Makefile and vcu118 ddr memory gen script.	2024-09-03 21:03:38 -07:00
insert_debug_comment.sh	Maded insert_debug_comment.sh compatible with cygwin.	2024-04-22 10:48:34 -05:00
Makefile	Fixed bugs in the fpga Makefile and vcu118 ddr memory gen script.	2024-09-03 21:03:38 -07:00
mmcm.tcl	Finally worked out that subtle bug in the tcl scripts clock setting.	2024-09-03 10:30:34 -07:00
probe	Update python shebangs to use /usr/bin/env python3 so virtual environment can be used (also aids in general portability)	2024-07-03 20:42:55 -07:00
sysrst.tcl	More updates to fpga IP module names.	2024-08-22 14:31:39 -07:00
wally.tcl	Added spi debugger to build script.	2024-09-05 12:04:14 -07:00
wave_config.wcfg	Updateds to vcu118 constraints and device tree.	2023-08-02 16:51:32 -05:00
xlnx_ddr3-artya7-mig.prj	It's almost working.	2023-04-18 14:24:59 -05:00
xlnx_ddr4.tcl	More updates to fpga IP module names.	2024-08-22 14:31:39 -07:00