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399 lines
10 KiB
Systemverilog
399 lines
10 KiB
Systemverilog
///////////////////////////////////////////
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// dcache (data cache) fsm
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//
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// Written: ross1728@gmail.com August 25, 2021
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// Implements the L1 data cache fsm
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//
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// Purpose: Controller for the dcache fsm
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module dcachefsm
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(input logic clk,
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input logic reset,
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// inputs from IEU
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input logic [1:0] LsuRWM,
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input logic [1:0] LsuAtomicM,
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input logic FlushDCacheM,
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// hazard inputs
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input logic CPUBusy,
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input logic CacheableM,
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// interlock fsm
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input logic IgnoreRequest,
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// Bus inputs
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input logic DCacheBusAck,
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// dcache internals
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input logic CacheHit,
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input logic VictimDirty,
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input logic FlushAdrFlag,
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// hazard outputs
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output logic DCacheStall,
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// counter outputs
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output logic DCacheMiss,
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output logic DCacheAccess,
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// Bus outputs
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output logic DCacheCommittedM,
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output logic DCacheWriteLine,
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output logic DCacheFetchLine,
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// dcache internals
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output logic [1:0] SelAdrM,
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output logic SetValid,
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output logic ClearValid,
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output logic SetDirty,
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output logic ClearDirty,
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output logic SRAMWordWriteEnableM,
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output logic SRAMLineWriteEnableM,
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output logic SelEvict,
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output logic LRUWriteEn,
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output logic SelFlush,
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output logic FlushAdrCntEn,
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output logic FlushWayCntEn,
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output logic FlushAdrCntRst,
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output logic FlushWayCntRst,
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output logic VDWriteEnable
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);
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logic AnyCPUReqM;
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typedef enum {STATE_READY,
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STATE_MISS_FETCH_WDV,
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STATE_MISS_FETCH_DONE,
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STATE_MISS_EVICT_DIRTY,
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STATE_MISS_WRITE_CACHE_LINE,
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STATE_MISS_READ_WORD,
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STATE_MISS_READ_WORD_DELAY,
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STATE_MISS_WRITE_WORD,
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STATE_CPU_BUSY,
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STATE_CPU_BUSY_FINISH_AMO,
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STATE_FLUSH,
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STATE_FLUSH_WRITE_BACK,
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STATE_FLUSH_CLEAR_DIRTY} statetype;
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(* mark_debug = "true" *) statetype CurrState, NextState;
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assign AnyCPUReqM = |LsuRWM | (|LsuAtomicM);
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// outputs for the performance counters.
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assign DCacheAccess = AnyCPUReqM & CacheableM & CurrState == STATE_READY;
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assign DCacheMiss = DCacheAccess & CacheableM & ~CacheHit;
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always_ff @(posedge clk)
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if (reset) CurrState <= #1 STATE_READY;
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else CurrState <= #1 NextState;
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// next state logic and some state ouputs.
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always_comb begin
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DCacheStall = 1'b0;
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SelAdrM = 2'b00;
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SetValid = 1'b0;
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ClearValid = 1'b0;
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SetDirty = 1'b0;
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ClearDirty = 1'b0;
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SRAMWordWriteEnableM = 1'b0;
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SRAMLineWriteEnableM = 1'b0;
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SelEvict = 1'b0;
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LRUWriteEn = 1'b0;
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SelFlush = 1'b0;
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FlushAdrCntEn = 1'b0;
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FlushWayCntEn = 1'b0;
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FlushAdrCntRst = 1'b0;
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FlushWayCntRst = 1'b0;
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VDWriteEnable = 1'b0;
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NextState = STATE_READY;
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DCacheFetchLine = 1'b0;
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DCacheWriteLine = 1'b0;
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case (CurrState)
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STATE_READY: begin
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DCacheStall = 1'b0;
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SelAdrM = 2'b00;
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SRAMWordWriteEnableM = 1'b0;
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SetDirty = 1'b0;
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LRUWriteEn = 1'b0;
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// TLB Miss
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if(IgnoreRequest) begin
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// the LSU arbiter has not yet selected the PTW.
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// The CPU needs to be stalled until that happens.
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// If we set DCacheStall for 1 cycle before going to
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// PTW ready the CPU will stall.
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// The page table walker asserts it's control 1 cycle
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// after the TLBs miss.
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SelAdrM = 2'b01;
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NextState = STATE_READY;
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end
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// Flush dcache to next level of memory
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else if(FlushDCacheM) begin
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NextState = STATE_FLUSH;
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DCacheStall = 1'b1;
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SelAdrM = 2'b10;
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FlushAdrCntRst = 1'b1;
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FlushWayCntRst = 1'b1;
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end
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// amo hit
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else if(LsuAtomicM[1] & (&LsuRWM) & CacheableM & CacheHit) begin
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SelAdrM = 2'b01;
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DCacheStall = 1'b0;
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if(CPUBusy) begin
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NextState = STATE_CPU_BUSY_FINISH_AMO;
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SelAdrM = 2'b01;
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end
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else begin
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SRAMWordWriteEnableM = 1'b1;
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SetDirty = 1'b1;
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LRUWriteEn = 1'b1;
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NextState = STATE_READY;
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end
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end
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// read hit valid cached
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else if(LsuRWM[1] & CacheableM & CacheHit) begin
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DCacheStall = 1'b0;
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LRUWriteEn = 1'b1;
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if(CPUBusy) begin
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NextState = STATE_CPU_BUSY;
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SelAdrM = 2'b01;
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end
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else begin
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NextState = STATE_READY;
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end
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end
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// write hit valid cached
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else if (LsuRWM[0] & CacheableM & CacheHit) begin
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SelAdrM = 2'b01;
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DCacheStall = 1'b0;
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SRAMWordWriteEnableM = 1'b1;
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SetDirty = 1'b1;
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LRUWriteEn = 1'b1;
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if(CPUBusy) begin
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NextState = STATE_CPU_BUSY;
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SelAdrM = 2'b01;
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end
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else begin
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NextState = STATE_READY;
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end
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end
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// read or write miss valid cached
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else if((|LsuRWM) & CacheableM & ~CacheHit) begin
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NextState = STATE_MISS_FETCH_WDV;
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DCacheStall = 1'b1;
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DCacheFetchLine = 1'b1;
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end
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else NextState = STATE_READY;
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end
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STATE_MISS_FETCH_WDV: begin
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DCacheStall = 1'b1;
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SelAdrM = 2'b01;
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if (DCacheBusAck) begin
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NextState = STATE_MISS_FETCH_DONE;
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end else begin
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NextState = STATE_MISS_FETCH_WDV;
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end
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end
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STATE_MISS_FETCH_DONE: begin
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DCacheStall = 1'b1;
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SelAdrM = 2'b01;
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if(VictimDirty) begin
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NextState = STATE_MISS_EVICT_DIRTY;
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DCacheWriteLine = 1'b1;
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end else begin
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NextState = STATE_MISS_WRITE_CACHE_LINE;
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end
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end
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STATE_MISS_WRITE_CACHE_LINE: begin
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SRAMLineWriteEnableM = 1'b1;
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DCacheStall = 1'b1;
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NextState = STATE_MISS_READ_WORD;
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SelAdrM = 2'b01;
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SetValid = 1'b1;
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ClearDirty = 1'b1;
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//LRUWriteEn = 1'b1; // DO not update LRU on SRAM fetch update. Wait for subsequent read/write
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end
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STATE_MISS_READ_WORD: begin
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SelAdrM = 2'b01;
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DCacheStall = 1'b1;
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if (LsuRWM[0] & ~LsuAtomicM[1]) begin // handles stores and amo write.
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NextState = STATE_MISS_WRITE_WORD;
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end else begin
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NextState = STATE_MISS_READ_WORD_DELAY;
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// delay state is required as the read signal LsuRWM[1] is still high when we
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// return to the ready state because the cache is stalling the cpu.
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end
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end
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STATE_MISS_READ_WORD_DELAY: begin
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//SelAdrM = 2'b01;
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SRAMWordWriteEnableM = 1'b0;
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SetDirty = 1'b0;
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LRUWriteEn = 1'b0;
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if(&LsuRWM & LsuAtomicM[1]) begin // amo write
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SelAdrM = 2'b01;
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if(CPUBusy) begin
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NextState = STATE_CPU_BUSY_FINISH_AMO;
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end
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else begin
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SRAMWordWriteEnableM = 1'b1;
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SetDirty = 1'b1;
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LRUWriteEn = 1'b1;
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NextState = STATE_READY;
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end
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end else begin
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LRUWriteEn = 1'b1;
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if(CPUBusy) begin
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NextState = STATE_CPU_BUSY;
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SelAdrM = 2'b01;
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end
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else begin
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NextState = STATE_READY;
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end
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end
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end
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STATE_MISS_WRITE_WORD: begin
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SRAMWordWriteEnableM = 1'b1;
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SetDirty = 1'b1;
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SelAdrM = 2'b01;
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LRUWriteEn = 1'b1;
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if(CPUBusy) begin
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NextState = STATE_CPU_BUSY;
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SelAdrM = 2'b01;
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end
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else begin
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NextState = STATE_READY;
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end
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end
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STATE_MISS_EVICT_DIRTY: begin
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DCacheStall = 1'b1;
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SelAdrM = 2'b01;
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SelEvict = 1'b1;
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if(DCacheBusAck) begin
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NextState = STATE_MISS_WRITE_CACHE_LINE;
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end else begin
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NextState = STATE_MISS_EVICT_DIRTY;
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end
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end
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STATE_CPU_BUSY: begin
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SelAdrM = 2'b00;
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if(CPUBusy) begin
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NextState = STATE_CPU_BUSY;
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SelAdrM = 2'b01;
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end
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else begin
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NextState = STATE_READY;
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end
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end
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STATE_CPU_BUSY_FINISH_AMO: begin
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SelAdrM = 2'b01;
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SRAMWordWriteEnableM = 1'b0;
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SetDirty = 1'b0;
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LRUWriteEn = 1'b0;
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if(CPUBusy) begin
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NextState = STATE_CPU_BUSY_FINISH_AMO;
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end
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else begin
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SRAMWordWriteEnableM = 1'b1;
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SetDirty = 1'b1;
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LRUWriteEn = 1'b1;
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NextState = STATE_READY;
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end
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end
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STATE_FLUSH: begin
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DCacheStall = 1'b1;
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SelAdrM = 2'b10;
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SelFlush = 1'b1;
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FlushAdrCntEn = 1'b1;
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FlushWayCntEn = 1'b1;
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if(VictimDirty) begin
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NextState = STATE_FLUSH_WRITE_BACK;
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FlushAdrCntEn = 1'b0;
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FlushWayCntEn = 1'b0;
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DCacheWriteLine = 1'b1;
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end else if (FlushAdrFlag) begin
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NextState = STATE_READY;
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DCacheStall = 1'b0;
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FlushAdrCntEn = 1'b0;
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FlushWayCntEn = 1'b0;
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end else begin
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NextState = STATE_FLUSH;
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end
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end
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STATE_FLUSH_WRITE_BACK: begin
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DCacheStall = 1'b1;
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SelAdrM = 2'b10;
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SelFlush = 1'b1;
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if(DCacheBusAck) begin
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NextState = STATE_FLUSH_CLEAR_DIRTY;
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end else begin
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NextState = STATE_FLUSH_WRITE_BACK;
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end
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end
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STATE_FLUSH_CLEAR_DIRTY: begin
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DCacheStall = 1'b1;
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ClearDirty = 1'b1;
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VDWriteEnable = 1'b1;
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SelFlush = 1'b1;
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SelAdrM = 2'b10;
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FlushAdrCntEn = 1'b0;
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FlushWayCntEn = 1'b0;
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if(FlushAdrFlag) begin
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NextState = STATE_READY;
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DCacheStall = 1'b0;
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SelAdrM = 2'b00;
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end else begin
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NextState = STATE_FLUSH;
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FlushAdrCntEn = 1'b1;
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FlushWayCntEn = 1'b1;
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end
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end
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default: begin
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NextState = STATE_READY;
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end
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endcase
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end
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assign DCacheCommittedM = CurrState != STATE_READY;
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endmodule // dcachefsm
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