Jordan Carlin 4a72922087 update config to derive MISA from macros ... - Remove C_SUPPORTED and update decompress unit based on Zc* extensions - Derive A_SUPPORTED from A subextensions - Derive B_SUPPORTED from B subextensions - Derive C_SUPPORTED from C subextensions		2024-05-14 06:49:18 -07:00
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checksignature.sv	Significant refactoring of testbench.	2023-06-14 17:02:49 -05:00
DCacheFlushFSM.sv	script cleanup	2024-04-20 17:22:31 -07:00
functionName.sv	Changed '0 to 0 where possible per Chapter 4 style guidelines	2024-03-06 05:48:17 -08:00
instrNameDecTB.sv	ZK cleanup, check no LLEN > XLEN without D$, add half and quad float load/store to instruction name decoder	2024-03-10 22:03:57 -07:00
instrTrackerTB.sv	moved riscvassertons to its own file, added proper license headers to testbench support files	2023-02-16 19:40:27 -08:00
loggers.sv	Pass TEST to testbench with +TEST=<name> rather than -G TEST=<name> so that we don't have to recompile for every new test	2024-04-06 10:34:21 -07:00
ramxdetector.sv	Yay! I got verilator to compile our testbench! Does it actually work I don't know.	2023-12-18 16:44:34 -06:00
riscvassertions.sv	update config to derive MISA from macros	2024-05-14 06:49:18 -07:00
wallyTracer.sv	Removed unused signals from WallyTracer	2024-04-30 08:54:28 -07:00
watchdog.sv	Changed '0 to 0 where possible per Chapter 4 style guidelines	2024-03-06 05:48:17 -08:00