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cvw/fpga/src
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Ross Thompson d2272c0620 Found and fixed the major architecture issue with the mig 7 used in the arty a7 board. 
mig 7 is completely different from the ddr4 mig in that the internal pll does not general the required clocks. An external mmcm is required to general two inputs clocks and the required user clock.
2023-04-15 11:13:28 -05:00
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fpgaTop.v Updated GPIO signal names to reflect book. 2023-03-24 18:55:43 -05:00
fpgaTopArtyA7.v Found and fixed the major architecture issue with the mig 7 used in the arty a7 board. 2023-04-15 11:13:28 -05:00