10 Commits

Author	SHA1	Message	Date
Ross Thompson	d2272c0620	Found and fixed the major architecture issue with the mig 7 used in the arty a7 board. ... mig 7 is completely different from the ddr4 mig in that the internal pll does not general the required clocks. An external mmcm is required to general two inputs clocks and the required user clock.	2023-04-15 11:13:28 -05:00
Ross Thompson	2abd164d03	Fixed syntax errors in arty7 top level.	2023-04-10 16:08:40 -05:00
Ross Thompson	81fb076e9e	Added more support for Arty A7 board.	2023-04-10 16:01:17 -05:00
Ross Thompson	78ab9f59af	Updated GPIO signal names to reflect book.	2023-03-24 18:55:43 -05:00
Ross Thompson	55335d1db6	Updated top level fpga file.	2022-11-18 11:10:45 -06:00
Ross Thompson	6250a65ede	added new constraints for fpga.	2022-09-17 22:20:06 -05:00
Ross Thompson	29743c5e9e	Fixed two issues. ... First the xci files already include the xdc constraints for each IP block. There is no need to include the xdc files explicitly. Second the bidir buffer for the sd card was connected backwards.	2021-12-07 12:15:50 -06:00
Ross Thompson	955ddcfbe1	Fixed bug in the top level of fpga verilog.	2021-12-03 17:55:36 -06:00
Ross Thompson	e94fb2aaec	Got fpga synthesis running from scripts.	2021-12-01 16:59:04 -06:00
Ross Thompson	5ea9ec0ae6	Created top level FPGA module which replicates the schematic of the initial fpga design.	2021-11-30 17:18:28 -06:00