cvw/pipelined/regression
2022-04-10 13:41:27 -05:00
..
slack-notifier Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
wave-dos
wkdir
buildrootBugFinder.py
fpga-wave.do Fixed the SDC clock divider so it actually can work during reset. This will enable the fpga to operate at a faster clock while the SDC is < 10Mhz. 2022-04-04 09:57:26 -05:00
lint-wally Added E tests to wally-riscv-arch-test rv32i_m/I and fixed cyclic path in rv32e configuration 2022-02-06 01:22:40 +00:00
linux-wave.do small signs of life on new interrupt spoofing 2022-04-08 12:32:30 -07:00
make-tests.sh
Makefile
makefile-memfile
regression-wally
sim-buildroot
sim-buildroot-batch
sim-coremark-batch Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
sim-fp64 Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
sim-fp64-batch Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
sim-wally
sim-wally-batch
wally-coremark.do Improve wavefile by adding performance counters. 2022-01-12 10:53:29 -06:00
wally-fp64-batch.do
wally-fp64.do Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
wally-harvard.do
wally-pipelined-batch.do
wally-pipelined-fpga.do fpga simulation works again. 2022-04-03 17:31:07 -05:00
wally-pipelined.do Modified the linux test bench to take a new parameter which can run simulation from 470M out to login prompt. This shouldn't break the regression test or checkpointing. 2022-04-10 13:27:54 -05:00
wave-all.do Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault. 2022-01-27 17:11:27 -06:00
wave-coremark.do More cache cleanup. 2022-02-13 15:47:27 -06:00
wave.do