Ross Thompson 79ec4161b6 Added more debugging code for FPGA.		2021-12-17 14:40:25 -06:00
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Makefile	Modified FPGA to add additional signals to ILA. Created advanced trigger for ILA using vivado's tsm language.	2021-12-12 17:21:44 -06:00
wally.tcl	Added more debugging code for FPGA.	2021-12-17 14:40:25 -06:00
xlnx_ahblite_axi_bridge.tcl	Created Makefile to manage IP generation.	2021-11-29 18:33:58 -06:00
xlnx_axi_clock_converter.tcl	Improved FPGA makefile and fixed timing constraints in clock converter.	2021-12-03 10:05:13 -06:00
xlnx_ddr4.tcl	Oups missed files in the last commit.	2021-12-15 10:25:08 -06:00
xlnx_proc_sys_reset.tcl	Created Makefile to manage IP generation.	2021-11-29 18:33:58 -06:00