cvw/pipelined/src
2023-01-06 00:09:18 -06:00
..
cache Minor optimizations. 2022-12-23 20:11:36 -06:00
ebu Success we've replaced TrapM with FlushD in the IFU. 2022-12-22 21:36:49 -06:00
fpu forgot the normshift module 2023-01-04 10:48:19 -06:00
generic Fixed problems with changes to ram2p. 2022-12-29 17:13:48 -06:00
hazard Minor optimizations. 2022-12-23 20:11:36 -06:00
ieu Handle special case Int Div/Rem of |A| < |B| in a single cycle 2023-01-01 13:54:01 -08:00
ifu Addd missing file. 2023-01-06 00:09:18 -06:00
lsu Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage. 2022-12-23 15:10:37 -06:00
mdu Renamed muldiv to mdu 2022-12-27 19:57:10 -08:00
mmu Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage. 2022-12-23 15:10:37 -06:00
ppa cleanup, plots for paper 2022-06-15 18:28:36 +00:00
privileged More branch predictor cleanup. 2023-01-05 17:19:27 -06:00
uncore Fixed minor bug in PLIC. reading interrupt source 0 should not return x. it should provide produce 0. 2022-12-21 09:00:09 -06:00
wally More branch predictor cleanup. 2023-01-05 17:19:27 -06:00
sdc piplined directory cleanup 2022-01-07 12:43:50 +00:00