13 Commits

Author	SHA1	Message	Date
James E. Stine	eb64a7f0c9	Update to fpdivsqrt to go on posedge as it should. Also an update to ... individual regression test for TestFloat (still needs some tweaking)	2021-10-13 17:14:42 -05:00
James E. Stine	b90d7b8083	Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat	2021-10-06 08:26:09 -05:00
Ross Thompson	3b12235954	Fixed FPGA synthesis bug in the fpdiv fsm. Was creating latches.	2021-09-11 15:40:27 -05:00
Katherine Parry	67ab0b165c	fpu cleanup	2021-07-24 14:59:57 -04:00
Katherine Parry	59f79722ab	FDIV and FSQRT work	2021-07-21 14:08:14 -04:00
James E. Stine	b36d6fe1be	slight mod to fpdiv - still bug in batch vs. non-batch	2021-07-20 01:47:46 -04:00
Katherine Parry	8d101548f1	FDIV and FSQRT passes when simulating in modelsim	2021-07-18 23:00:04 -04:00
Katherine Parry	3527620c0b	fdivsqrt inegrated, but not completley working	2021-07-18 14:03:37 -04:00
Katherine Parry	b55798f09b	lint is clean	2021-06-07 14:22:54 -04:00
Katherine Parry	e4db6ea6f5	fixed lint warnings for fpu and lzd	2021-06-05 12:06:33 -04:00
Katherine Parry	71e4a10efb	FMV.D.X imperas test passes	2021-05-20 22:17:59 -04:00
Katherine Parry	9252d08b41	fpu imperas tests run	2021-05-01 02:18:01 +00:00
Katherine Parry	f41b5a2d38	Added missing files in FPU	2021-04-04 18:09:13 +00:00