David Harris
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95407a6ea7
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Replaced && and || with & and | in non-fp files per new style guidelines
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2022-01-02 21:47:21 +00:00 |
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David Harris
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77c00e996b
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Started adding asynchronous TIMECLK for CLINT
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2022-01-02 21:18:16 +00:00 |
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Katherine Parry
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cf7aa4e8ae
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some errors in FP ArchTests fixed
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2022-01-01 23:50:23 +00:00 |
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David Harris
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ae3767bd54
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-12-31 06:40:25 +00:00 |
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David Harris
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62e6aed7e5
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Simplified performance counters
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2021-12-31 06:40:21 +00:00 |
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Ross Thompson
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2096d45c23
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-12-30 18:10:36 -06:00 |
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Ross Thompson
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89dc598a83
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Patched up the linux-wave.do file.
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2021-12-30 17:53:43 -06:00 |
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David Harris
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19a47bd276
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-12-30 23:40:02 +00:00 |
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David Harris
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4066ea6463
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Fixes to counters; buildroot still broken
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2021-12-30 23:39:59 +00:00 |
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Ross Thompson
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fd77022f73
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No dcache now supported. Does not pass regression tests however.
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2021-12-30 15:26:32 -06:00 |
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David Harris
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451f37729f
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Added names to generate blocks
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2021-12-30 20:55:48 +00:00 |
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David Harris
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e084c8868f
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Added wally-riscv-arch-test MMU tests and removed imperas MMU tests from regresssion
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2021-12-30 17:22:18 +00:00 |
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Ross Thompson
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e506957790
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Updated lsu so it is possible to condictionally implement dcache or passthrough to ebu.
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2021-12-29 22:24:37 -06:00 |
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David Harris
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c6f4a15bfb
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Fixed generate statement name in csrm for buildroot regression
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2021-12-30 03:01:21 +00:00 |
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David Harris
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26d6f8d51a
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RV32ic tests running for simple machine with no privileged unit
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2021-12-30 02:25:46 +00:00 |
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David Harris
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866a5efc43
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rv32i regression and linting
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2021-12-30 00:53:39 +00:00 |
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Ross Thompson
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aa227ce97c
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Changed names of lsu address signals.
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2021-12-29 15:03:34 -06:00 |
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Ross Thompson
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e36a037afa
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Added more generates around virtual memory and csrs in the lsu.
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2021-12-29 14:48:09 -06:00 |
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David Harris
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d78b806332
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Added performance counting to sumtest and added imperas32/64periph to testbench.
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2021-12-29 00:28:51 +00:00 |
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David Harris
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69243f41ad
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Fixed imperas C tests
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2021-12-26 04:45:06 +00:00 |
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David Harris
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a7cfda8e52
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Incorporated new Imperas tests. f and d tests are failing and c tests are hanging.
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2021-12-26 04:36:53 +00:00 |
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David Harris
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e97e512da9
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Started FIR test code and started incorporating Imperas tests
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2021-12-25 22:39:51 +00:00 |
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Ross Thompson
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47638cdccf
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Looks like rdtime was accidentally replaced with rrame from a find and replace.
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2021-12-20 21:26:38 -06:00 |
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David Harris
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193885c958
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Moved generate of conditional units to hart
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2021-12-19 17:03:57 -08:00 |
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David Harris
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1196e5c191
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Moved generate statements for optional units into wallypipelinedhart
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2021-12-19 16:53:41 -08:00 |
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Ross Thompson
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7b2f5440a5
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Changes to buildroot to support MemAdrM to IEUAdrM name changes.
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2021-12-19 18:24:40 -06:00 |
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David Harris
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3a9071e509
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Renamed MemAdrE to IEUAdrE and moved the MemAdrM flop from IEU to LSU to reduce wires crossing hierarchies
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2021-12-15 12:10:45 -08:00 |
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David Harris
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f4957fdac1
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Renamed dtim->ram and boottim ->bootrom
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2021-12-14 13:43:06 -08:00 |
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David Harris
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dd0d4c0add
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ALU and datapath cleanup
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2021-12-14 11:15:47 -08:00 |
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David Harris
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74cf0eb96a
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-12-13 07:57:49 -08:00 |
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David Harris
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1ca949c0bb
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Simplified ALU and source multiplexers pass tests
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2021-12-13 07:57:38 -08:00 |
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Kevin
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b928d01bb8
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dot stars conversions on the rest of the testbenches
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2021-12-12 17:53:26 -08:00 |
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Kevin
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78fbe542a9
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edited one testbench, yet to run regression
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2021-12-10 20:26:20 -08:00 |
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bbracker
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c97e96f553
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-12-08 14:12:09 -08:00 |
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bbracker
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6a6835ddc3
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fix release of ReadDataM
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2021-12-08 14:11:43 -08:00 |
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Ross Thompson
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37451b8978
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-12-08 13:40:44 -06:00 |
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Ross Thompson
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e1249f4312
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Updated coremark testbench with the extra ports from FPGA merge.
Fixed coremark Makefile to create work directory.
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2021-12-08 13:40:32 -06:00 |
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bbracker
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0c48725fa5
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fix checkpointing so that it can find the synchronized reset signal
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2021-12-07 13:12:06 -08:00 |
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Skylar Litz
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a69ab3bd1b
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fix some interrupt timing bugs
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2021-12-03 12:32:38 -08:00 |
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Ross Thompson
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755c3e6a4c
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Fixed buildroot to work with the fpga's merge.
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2021-12-02 18:09:43 -06:00 |
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Ross Thompson
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74ffb48c0a
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Mostly integrated FPGA flow into main branch. Not all tests passing yet.
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2021-12-02 18:00:32 -06:00 |
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Ross Thompson
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8e4eacc18e
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Merge branch 'main' into fpga
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2021-11-29 10:10:37 -06:00 |
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Ross Thompson
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e43aa6ead4
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Merge branch 'main' into fpga
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2021-11-29 10:06:53 -06:00 |
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bbracker
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c5d393fbc6
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UART hack now looks at physical addresses so that it isn't bamboozled by S-mode accesses
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2021-11-25 11:01:59 -08:00 |
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bbracker
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d90d708cf9
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activate STVAL for buildroot
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2021-11-21 10:40:28 -08:00 |
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David Harris
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fb3f267645
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Coremark Cleanup, trying compile from addins
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2021-11-19 06:09:04 -08:00 |
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David Harris
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d243f4bcd1
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Cleaning up CoreMark benchmark
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2021-11-18 20:12:52 -08:00 |
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David Harris
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54fef3e2ca
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vert "Simplifying riscv-coremark"
This reverts commit bdc212cf88.
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2021-11-18 18:40:13 -08:00 |
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David Harris
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bdc212cf88
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Simplifying riscv-coremark
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2021-11-18 17:15:40 -08:00 |
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David Harris
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b996598b37
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CoreMark testing
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2021-11-18 16:14:25 -08:00 |
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