David Harris
10549b7787
Completed basic tests of svnapot and svpbmt
2023-08-28 06:57:35 -07:00
David Harris
75986d6641
Fixed merge conflict for ZICBOP
2023-08-25 18:41:57 -07:00
David Harris
9f44241d0f
Added N and PBMT bits to MMU PTE
2023-08-24 19:44:46 -07:00
Ross Thompson
c114d3a07d
Added rv32 cboz test.
2023-08-24 17:02:53 -05:00
Ross Thompson
e8bc339638
Oups there was a bug in the SATP fix. RV32GC was broken by the changes.
2023-08-23 09:42:46 -05:00
David Harris
38e437c724
Merge pull request #383 from ross144/main
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Adds Zicbom support for D-cache only. I-cache not yet supported. Tests 32 and 64 bit versions. Please rebuild regressions wally32 and wally64. To save rebuild time edit lines 11-12 of tests/riscof/Makefile
2023-08-21 13:32:00 -07:00
Ross Thompson
168ef0ab53
Have a working 32 bit cbom test!
2023-08-21 13:46:09 -05:00
Ross Thompson
6ffbdaac0a
Working CBO tests for 64 bit!
2023-08-21 12:55:07 -05:00
David Harris
36a825c43b
Improved CSRU coverage with priv.S
2023-08-20 12:49:31 -07:00
Ross Thompson
3eeecd2f27
Merge branch 'boot' into mergeBoot
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Merges Jacob's new sdc controller into wally.
2023-07-21 17:43:45 -05:00
Ross Thompson
2854452ecc
Removed all old configuration files.
2023-07-19 10:28:54 -05:00
Ross Thompson
3bf2b35704
Wow. The newest version of Vivado does not like the enums as parameters.
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The solution is simple. I changed the type to logic [31:0] and defined macros for the branch predictor types as 32 bit integers.
2023-07-18 15:07:10 -05:00
Ross Thompson
6ddd8d4e2b
Fixed the icache and dcache overlogging issue.
2023-07-14 15:47:05 -05:00
Ross Thompson
add1a6996e
Merge branch 'main' of github.com:ross144/cvw
2023-07-11 15:09:07 -05:00
Ross Thompson
f30c92e82a
Added wfi and interrupt to tracer.
2023-07-11 15:09:04 -05:00
Ross Thompson
58dfc15844
Merge branch 'main' of github.com:ross144/cvw into main
2023-07-11 15:08:26 -05:00
Ross Thompson
c12bc4f435
Created separate temporary testbench for xcelium.
2023-07-11 15:07:33 -05:00
Ross Thompson
b26dc6db7f
Simplificaiton of function tracker.
2023-07-11 10:51:17 -05:00
Ross Thompson
4e54e5169b
Changes for xcelium.
2023-07-07 18:22:28 -05:00
Ross Thompson
74834bde2c
Removed duplicate signal name from testbench.
2023-07-07 16:34:08 -05:00
Ross Thompson
0394f3232f
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-07-06 14:55:43 -05:00
David Harris
34ce25ca81
Commented SVADU requirements for wally32priv mmu tests
2023-07-04 11:34:07 -07:00
David Harris
4c921fc797
Added logic to warn about x in memory reads. Added cbo instruction names to testbench decoder
2023-07-02 13:29:27 -07:00
James E. Stine
407bf44548
Modification (temporary) to testbench-fp.sv to allow testing of anything FMA. This might need to be changed with OpCtrl to make more robust for future expansion.
2023-06-29 08:46:11 -05:00
James E. Stine
012316aa94
Minor tweak to fix vectors not working for fadd.
2023-06-26 14:25:44 -05:00
James E. Stine
83a79b3a40
Fix items related to testing of TestFloat that were not always matching. The issue resulted due to the repeat statement that interferes with the always block. I separated the two to allow them to work correctly
2023-06-26 10:14:49 -05:00
James E. Stine
e913c1ea46
Modify testbench-fp.sv to handle parameterization as well some other minor mods. Have to make a better FPUActive desgination but for now works
2023-06-22 15:27:17 -05:00
James E. Stine
394c7ac9af
Update sim-testfloat to fix errors due to bad config element. I am not sure of the reasoning, but the specific path to the testvector was not getting inserted in Questa. This modification also adds features to test individualized tests (.e.g, binary16 only) -- documentation is added in the FPbuild.txt file
2023-06-20 17:26:54 -05:00
Ross Thompson
626a918668
FPGA updates.
2023-06-20 11:11:34 -05:00
Ross Thompson
1d2eb60ffb
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-06-18 16:37:19 -05:00
David Harris
60931e7d5c
Fixed embench to run all tests, even ones not in 1.0
2023-06-17 20:38:51 -07:00
David Harris
e2f927b4e6
Replaced zext.h with zext.h_64 in rv64 tests because old one is obsolete
2023-06-16 16:07:28 -07:00
Ross Thompson
4bee446cad
Vivado requires an intermediate wrapper file for parameterization.
2023-06-16 16:30:14 -05:00
David Harris
dfedc13cfc
erge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-06-16 10:32:37 -07:00
David Harris
281c036e70
Merge pull request #342 from ross144/main
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Testbench generates embench output files
2023-06-16 10:32:18 -07:00
Ross Thompson
509aee36ef
Modified the testbench to generate the required files for embench scripts.
2023-06-16 12:27:22 -05:00
David Harris
2d94800ad7
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-06-16 10:03:48 -07:00
David Harris
1cb0cf38b4
Merge pull request #341 from ross144/main
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Fix embench so it does not crash
2023-06-16 10:03:41 -07:00
Ross Thompson
3f628d6bf2
embench testbench no longer crashes.
2023-06-16 11:54:41 -05:00
David Harris
3c98ed9e29
Added assertions for ZICNTR and ZIHPM
2023-06-16 09:26:02 -07:00
eroom1966
9125f25880
add changes for latest IDV file layout
2023-06-16 16:43:53 +01:00
Ross Thompson
605ddf7990
Fixed the imperas testbench to work with parameters.
2023-06-16 08:59:52 -05:00
Ross Thompson
110a41c046
Have the linux testbench working in the mean time. Before the consolidation.
2023-06-15 16:18:37 -05:00
Ross Thompson
34d1d50b87
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-06-15 15:38:38 -05:00
Ross Thompson
a011b7d591
Merge branch 'testbench-params2'
2023-06-15 15:31:13 -05:00
Ross Thompson
a55bcad5c1
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-06-15 14:57:23 -05:00
Ross Thompson
3c4677ef63
Major cleanup of testbench.
2023-06-15 14:57:05 -05:00
Ross Thompson
44c72c20e2
Actually removed old `define configuration file for rv64gc. There were a lot of dangling problems.
2023-06-15 14:05:44 -05:00
Ross Thompson
e431f90cf3
Found a whole bunch of files still using the old `define configurations.
2023-06-15 13:09:07 -05:00
David Harris
bcb9c242d4
Added BMU instructions to instruction name decoder
2023-06-15 09:26:09 -07:00
